How to use a Side-Brazed Dual In-Line Ceramic Package

Discussion in 'General Electronics Discussion' started by Chengjun Li, Aug 9, 2016.

  1. Chengjun Li

    Chengjun Li

    Oct 21, 2014
    Likes Received:
    I have a silicon chip which has a built in capacitor pair. I use a Side-Brazed Dual In-Line Ceramic Package(shown below) to carry the chip. Wire bonding is used to connect the chip and package.
    upload_2016-8-9_16-35-55.png is the link to the package.

    I connect the package to an external board to measure the differential capacitance of the capacitor pair on the silicon chip. However, the output voltage of the external board drift seriously.

    The external board works by applying a square wave to the capacitor pair. I found that the pads or pins next to the ones which I apply the square wave to also have certain alternating voltage(as large as 0.5V), which I suppose should be zero volt ideally.

    I wonder is this induced alternating voltage the reason I got drifting capacitance measurement result?And how to solve it.
    Chengjun Li, Aug 9, 2016
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  2. Chengjun Li

    Harald Kapp Moderator Moderator

    Nov 17, 2011
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    Germany-Europe-Earth-Sol System-Milky Way-Laniakea
    You'll have stray capacitances from the package and the board which will influence your measurements, even more so as the capacitances on the silicon die are probably on the same order or even smaller than the capacitances from the package and board.
    A standadrd measure to minimize the influence of these stray capacitances is a driven guard (see ref. 3): you apply a voltage of the same potential as the pin to be measured to the surrounding pins. Thereby the voltage between the measured pin and the surrounding pins is 0 V and the effect of the stray capacitances is minimized.
    Harald Kapp, Aug 10, 2016
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  3. Chengjun Li


    Jan 15, 2010
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    I'm unclear as to your actual physical construction of your assembly here.
    Harald's advice on 'guarding' the IC is pretty standard.
    I'm wondering however, if your construction technique is contributing to your problem.
    You say you have a built-in capacitor pair, a side-brazed ceramic DIP package, and then talk about
    wire-bonding to connect the chip and the package.
    I don't understand what you actually have there.
    Usually, I've seen external capacitors installed in IC sockets. Is/are your built-in capacitor pair actually
    integral to the IC, or are they externally connected.
    I also am unclear about your use of wire-bonding in this project. That's the equivalent of arc-welding,
    and should never be attempted with an IC itself.
    Have you got a picture of your complete assembly?
    I'm wondering if maybe your components themselves have some damage from the assembly process.
    shrtrnd, Aug 10, 2016
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