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How to solve Protel "Warning - net contains unplated pads" ?

Dear Sir:
When I DRC in Protel DXP I get much this message
"[Un-Routed Net Constraint Violation] PCB1_998.PcbDoc Advanced PCB Net
DSP_AAOE
Warning - net contains unplated pads "

Someone can help me? thanks a lot!
 
G

Graham Holloway

Jan 1, 1970
0
Dear Sir:
When I DRC in Protel DXP I get much this message
"[Un-Routed Net Constraint Violation] PCB1_998.PcbDoc Advanced PCB Net
DSP_AAOE
Warning - net contains unplated pads "

Someone can help me? thanks a lot!

I suspect that your routing involves a track that passes though a pad from
one layer to another. Verify that the pad(s) involved are plated through.

Graham Holloway
WPS/Accuphon Audio
 
P

Peter Bennett

Jan 1, 1970
0
Dear Sir:
When I DRC in Protel DXP I get much this message
"[Un-Routed Net Constraint Violation] PCB1_998.PcbDoc Advanced PCB Net
DSP_AAOE
Warning - net contains unplated pads "

Someone can help me? thanks a lot!

Find the guilty pads and make them plated....

In Protel, even surface mount pads must be declared as "plated", with
a hole size of zero.




--
Peter Bennett, VE7CEI
peterbb4 (at) interchange.ubc.ca
new newsgroup users info : http://vancouver-webpages.com/nnq
GPS and NMEA info: http://vancouver-webpages.com/peter
Vancouver Power Squadron: http://vancouver.powersquadron.ca
 
Thanks Graham Holloway and Peter Bennett.
The problem had solved just as you said.

I have a new problem in DRC message
"Warning - Pad/Via touching plane splitting primitives"
Although I can disenable this option in DRC'option,But I want to know
if this is a really problem.
Can someone give me some advisement. Thanks
 
S

Simon Peacock

Jan 1, 1970
0
you will have to look and see if its a problem. Usually they aren't, but
its best to move the split plane boarder by 10 thou to get rid of the error
so the next guy doesn't get it too.

And you should never disable DRC options.. except for component clearance
and acute angles.

Simon
 
P

Peter Bennett

Jan 1, 1970
0
you will have to look and see if its a problem. Usually they aren't, but
its best to move the split plane boarder by 10 thou to get rid of the error
so the next guy doesn't get it too.

And you should never disable DRC options.. except for component clearance
and acute angles.

It is sometimes impossible to get rid of all DRC errors. It is OK to
have some on a finished board, as long as you know _why_ they are
there, and are sure the board is the way you want.

Having DRC errors does not prevent you from finishing the design
process and producing Gerber and drill files.
 
S

Simon Peacock

Jan 1, 1970
0
True.. I often have 4 or 5.. but as you say.. each is documented.

One thing I'd like to see in the schematic ERC is the ability to put a
limited "no-erc" marker.. for example.. "no-erc-if-pin-not-connected" so
that anything other than not connected is an error.. in fact.. the pin
connected is also an error (invert the warning status)

Simon
 
B

Brad Velander

Jan 1, 1970
0
Hey Simon, Peter,
Are you forgetting something or has it been corrected in DXP
( and does the user have the DXP SP# that solved the issue). The
connection issues with pads or vias on a split plane boundary? It
either doesn't connect or shorts the two split planes together,
remember? Then considering the split plane has calculated
negative image connections and ties you can't actually get a true
DRC determination on the issue.

The original poster needs to know precisely where that DRC is
originating (or multiple locations) and then either fix it by
moving the split plane boundary or at the very least manually
inspect the Gerbers very closely at those locations to make sure
there isn't an unexpected disconnect or short at those points. I
would go for moving it rather than waiting for Gerbers and then
finding out you had to move it anyway after it means more work to
move it. Or he could test the Gerbers now and pray it didn't
change at all in the final board because of some further
interactions with other file details.

--
Sincerely,
Brad Velander

Simon Peacock said:
True.. I often have 4 or 5.. but as you say.. each is documented.

One thing I'd like to see in the schematic ERC is the ability to put a
limited "no-erc" marker.. for example..
"no-erc-if-pin-not-connected" so
 
S

Simon Peacock

Jan 1, 1970
0
good point.. I've never seen this particular bug as I always make sure
there's no plane connected via thru a split plane boundary. 99SE suffered a
similar fate from memory with direct connected vias.

Simon
 
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