C
Chris Carlen
- Jan 1, 1970
- 0
Greetings:
I am considering the use of the IR2125 instead of the IR2110, if I can
understand the current sensing circuitry of the IR2125 and can conclude
that I want to have that feature.
Taking a look at the IR2125 datasheet:
http://www.irf.com/product-info/datasheets/data/ir2125.pdf
We find that the "typical connection" shown on the front page involves a
4-terminal MOSFET. I gather that for such a device, the gate charge
flows into the gate and out the source, bypassing the current sense
resistor and so not producing a spike in the current sense terminal.
The load current flows out of the bottom terminal, whatever it might be
called, through the current sense resistor.
In this illustration, the current sense voltage is developed positive
with respect to the source voltage.
Looking then at the functional diagram on page 4 we see things don't
quite add up. There is a .23V offset voltage source connected with its
positive terminal on the Vs pin of the IC, and the negative terminal on
the inverting input to the "amplifier." Thus, if the voltage drop
across the current sense resistor is zero in the resting state, then the
amplifier should output a high level.
Now if the load current flows through the current sense resistor as
shown on the front page, then the voltage developed at the CS pin with
respect to the Vs pin will be positive, in which case it simply adds to
the 0.23V offset, and no change in the output of the amplifier would
ever be produced as a result of load current. (Assuming a high gain
amplifier, saturated output. The gain of the amplifier is not specified
in the datasheet.)
It must be that the diagram shows the offset voltage's polarity
backwards, and that in fact the voltage is positive 0.23V at the
inverting input of the amplifier. This would mean that a CS voltage of
threshold, why on earth would one want to apply a high level to the
lower contact of the switch located at the input to the buffer?
This brings us to the question of what the comparator is supposed to do.
Again things don't make much sense if the 0.23V polarity is as
shown, because then the comparator won't do anything unless the CS goes
negative, which isn't allowed by the ratings, and won't happen according
to the connection diagram when load current flows.
0. Is the 0.23V source shown with the wrong polarity?
So once again I am left to conclude that the 0.23V must be the other way
around, with negative terminal really connected to Vs, and positive
terminal to the comparator input. Ok, then if CS rises to >0.23V the
comparator switches. What then?
1. What is the 500ns blank function? Is it to filter out gate
switching spikes (when using normal 3-terminal instead of 4-terminal
devices) so they don't cause unintended turn-offs?
Assuming that the blank function means nothing happens unless the CS >
0.23V condition is met for more than 500ns before the comparator
transistion is passed through, then the switch gets thrown to the lower
contact, which doesn't bring the output low because the lower contact is
held high by the amplifier when CS > Vs + 0.23V.
2. Is the amplifier input polarity also written backwards?
I figured the point of the little switch was so that the current sense
could shut down the output more quickly than would be possible by
waiting for the propagation through the down level shifter and logic,
then back up through the up level shifter. But if that is the point of
the switch, why have its lower contact connected to the amplifier's high
output? Why not connect it simply to a low level like Vs? Unless of
course the amplifier is indeed labeled wrong. Ugh!
Assuming we agree that the 0.23 is backwards, and so is the amplifier
input polarity labels, then things begin to make sense. CS>0.23V makes
the amplifier output swing low. Then the comparator switches, but the
500ns wait happens. If we had only a gate charging spike, the amplifier
and comparator switch back and nothing happens. But if we have a real
overcurrent, then the comparator is still switched after 500ns, so the
switch before the buffer connects the output to the low output of the
amp, turning off the MOSFET. Meanwhile the comparator signal propagates
through the rest of the chip to latch the error condition.
The only remaining problem is how to explain the waveforms shown in
figure 1, specifically the part where the CS level makes transistions.
This diagram seems to indicate that a very short CS pulse only causes
the output to go low for the duration of the CS pulse, not latching it
low until the next rising input pulse. This doesn't seem very useful.
Finally, what's the deal with the 4-terminal MOSFET? Does such a thing
exist?
Comments appreciated.
Good day!
--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
I am considering the use of the IR2125 instead of the IR2110, if I can
understand the current sensing circuitry of the IR2125 and can conclude
that I want to have that feature.
Taking a look at the IR2125 datasheet:
http://www.irf.com/product-info/datasheets/data/ir2125.pdf
We find that the "typical connection" shown on the front page involves a
4-terminal MOSFET. I gather that for such a device, the gate charge
flows into the gate and out the source, bypassing the current sense
resistor and so not producing a spike in the current sense terminal.
The load current flows out of the bottom terminal, whatever it might be
called, through the current sense resistor.
In this illustration, the current sense voltage is developed positive
with respect to the source voltage.
Looking then at the functional diagram on page 4 we see things don't
quite add up. There is a .23V offset voltage source connected with its
positive terminal on the Vs pin of the IC, and the negative terminal on
the inverting input to the "amplifier." Thus, if the voltage drop
across the current sense resistor is zero in the resting state, then the
amplifier should output a high level.
Now if the load current flows through the current sense resistor as
shown on the front page, then the voltage developed at the CS pin with
respect to the Vs pin will be positive, in which case it simply adds to
the 0.23V offset, and no change in the output of the amplifier would
ever be produced as a result of load current. (Assuming a high gain
amplifier, saturated output. The gain of the amplifier is not specified
in the datasheet.)
It must be that the diagram shows the offset voltage's polarity
backwards, and that in fact the voltage is positive 0.23V at the
inverting input of the amplifier. This would mean that a CS voltage of
But this doesn't make much sense, because if the current exceeded the
threshold, why on earth would one want to apply a high level to the
lower contact of the switch located at the input to the buffer?
This brings us to the question of what the comparator is supposed to do.
Again things don't make much sense if the 0.23V polarity is as
shown, because then the comparator won't do anything unless the CS goes
negative, which isn't allowed by the ratings, and won't happen according
to the connection diagram when load current flows.
0. Is the 0.23V source shown with the wrong polarity?
So once again I am left to conclude that the 0.23V must be the other way
around, with negative terminal really connected to Vs, and positive
terminal to the comparator input. Ok, then if CS rises to >0.23V the
comparator switches. What then?
1. What is the 500ns blank function? Is it to filter out gate
switching spikes (when using normal 3-terminal instead of 4-terminal
devices) so they don't cause unintended turn-offs?
Assuming that the blank function means nothing happens unless the CS >
0.23V condition is met for more than 500ns before the comparator
transistion is passed through, then the switch gets thrown to the lower
contact, which doesn't bring the output low because the lower contact is
held high by the amplifier when CS > Vs + 0.23V.
2. Is the amplifier input polarity also written backwards?
I figured the point of the little switch was so that the current sense
could shut down the output more quickly than would be possible by
waiting for the propagation through the down level shifter and logic,
then back up through the up level shifter. But if that is the point of
the switch, why have its lower contact connected to the amplifier's high
output? Why not connect it simply to a low level like Vs? Unless of
course the amplifier is indeed labeled wrong. Ugh!
Assuming we agree that the 0.23 is backwards, and so is the amplifier
input polarity labels, then things begin to make sense. CS>0.23V makes
the amplifier output swing low. Then the comparator switches, but the
500ns wait happens. If we had only a gate charging spike, the amplifier
and comparator switch back and nothing happens. But if we have a real
overcurrent, then the comparator is still switched after 500ns, so the
switch before the buffer connects the output to the low output of the
amp, turning off the MOSFET. Meanwhile the comparator signal propagates
through the rest of the chip to latch the error condition.
The only remaining problem is how to explain the waveforms shown in
figure 1, specifically the part where the CS level makes transistions.
This diagram seems to indicate that a very short CS pulse only causes
the output to go low for the duration of the CS pulse, not latching it
low until the next rising input pulse. This doesn't seem very useful.
Finally, what's the deal with the 4-terminal MOSFET? Does such a thing
exist?
Comments appreciated.
Good day!
--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
[email protected]
