M
[email protected]
- Jan 1, 1970
- 0
Can anyone please help me understand the relationship between a FET's
saturation region and the saturation
point of a power amplifier? From what I have read, the FET has three
regions of operation: ohmic, saturation and cut-off. The description
of the cut-off region seems the most straightforward:
Vgs < Vthreshold, Ids = 0, i.e. no current flow, so the Power
amplifier is like an open switch.
In the ohmic region:
Vgs > Vthreshold, Ids ~ (Vgs - Vthreshold)*Vds. Ids is dependent on
Vds, the Power amplifer is like a voltage controlled resistor.
I don't understand the purpose of the ohmic region from a power
amplification perspective, but it is the saturation region that really
has me confused. In saturation:
Vgs > Vthreshold, Ids ~ (Vgs - Vthreshold)^2. Ids does not depend on
Vds, but increases as Vgs increases.
As I understand it, this is called the 'saturation region' of the FET
because for any particular value of Vgs, Ids is constant for all
values of Vds > Vgs - Vthreshold. So Ids is saturated.
What I can't figure out is, at what point does a power amplifier
biased in the FET saturation region become saturated i.e. when the
power amplifier reaches its maximum output power and begins to
compress? If you plot Ids against Vgs you get like a rising
exponential. My thinking is that the part of the exponential where the
slope is zero corresponds to the power amplifier saturation. Is this
logical?
Any suggestions welcome.
Thanks
mees
saturation region and the saturation
point of a power amplifier? From what I have read, the FET has three
regions of operation: ohmic, saturation and cut-off. The description
of the cut-off region seems the most straightforward:
Vgs < Vthreshold, Ids = 0, i.e. no current flow, so the Power
amplifier is like an open switch.
In the ohmic region:
Vgs > Vthreshold, Ids ~ (Vgs - Vthreshold)*Vds. Ids is dependent on
Vds, the Power amplifer is like a voltage controlled resistor.
I don't understand the purpose of the ohmic region from a power
amplification perspective, but it is the saturation region that really
has me confused. In saturation:
Vgs > Vthreshold, Ids ~ (Vgs - Vthreshold)^2. Ids does not depend on
Vds, but increases as Vgs increases.
As I understand it, this is called the 'saturation region' of the FET
because for any particular value of Vgs, Ids is constant for all
values of Vds > Vgs - Vthreshold. So Ids is saturated.
What I can't figure out is, at what point does a power amplifier
biased in the FET saturation region become saturated i.e. when the
power amplifier reaches its maximum output power and begins to
compress? If you plot Ids against Vgs you get like a rising
exponential. My thinking is that the part of the exponential where the
slope is zero corresponds to the power amplifier saturation. Is this
logical?
Any suggestions welcome.
Thanks
mees