Designing the right clock tree for a multi-FPGA setup

[Geronimo Stempovski]

Hi folks,

I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some
periphery. The three FPGAs are needed due to the data processing complexity
and the amount of high-speed IOs (MGTs). What I am most concerned about
right now is to find an appropriate clocking solution.

In my opinion, there are mainly three alternatives to design the clocking
scheme:

a) connection of the clock in a star-like topology, feeding each of the
three FPGAs with the same clock signal (which has to be possibly duplicated
by a clock buffer to generate three out of one clock reference signal,
thereby introducing additional jitter)

b) clock in daisy-chain, feeding each of the three FPGAs with the identical
clock signal which is routed from one device to another (in terms of jitter
this is also not an optimal solution)

c) each FPGA device is supplied with its own clock (which than can be
optimally routed to the device in short distances), but synchronization is a
major issue then

Does anyone have sufficient experience in designing clock trees and is
willing to share his experience, comments, hints and suggestions with me?

Thanks in advance

Gero

 

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| a) connection of the clock in a star-like topology, feeding each of the
| three FPGAs with the same clock signal (which has to be possibly duplicated
| by a clock buffer to generate three out of one clock reference signal,
| thereby introducing additional jitter)

Do you really need it buffered for isolation? If you have enough clock
power, could you not feed all three from the one clock with impedance
matched lines? What is the frequency, anyway?

 

[John Larkin]

Hi folks,

I am planning to design a PCB featuring three Virtex-4 FX60 FPGAs and some
periphery. The three FPGAs are needed due to the data processing complexity
and the amount of high-speed IOs (MGTs). What I am most concerned about
right now is to find an appropriate clocking solution.

In my opinion, there are mainly three alternatives to design the clocking
scheme:

a) connection of the clock in a star-like topology, feeding each of the
three FPGAs with the same clock signal (which has to be possibly duplicated
by a clock buffer to generate three out of one clock reference signal,
thereby introducing additional jitter)

b) clock in daisy-chain, feeding each of the three FPGAs with the identical
clock signal which is routed from one device to another (in terms of jitter
this is also not an optimal solution)

c) each FPGA device is supplied with its own clock (which than can be
optimally routed to the device in short distances), but synchronization is a
major issue then

Does anyone have sufficient experience in designing clock trees and is
willing to share his experience, comments, hints and suggestions with me?

Thanks in advance

Gero

The most conservative way to do this would be to use three LVDS
drivers at the oscillator (or one of those new fancy LVDS clock
driver/tweaker chips), go differential star-routed to each chip, and
terminate at each one. Most FPGAs accept differential clocks these
days. That said, it's still a good idea to route the diff clock traces
carefully, low-skew, good impedance control, and away from any
crosstalk aggressors.

We also like to use a fast, hard 3.3 volt single-ended driver, source
terminated, and put a tiny logic schmitt trigger at the other end,
right next to the fpga clock input. FPGA clock inputs tend to have
little or no edge-noise immunity, and are hyper-delicate, so the
schmitt really helps if you're not running super fast and can tolerate
the added delay.

Long single-trace daisy chains are the riskiest, unless you regenerate
the clock at every way-station.

John