K
Keith M
- Jan 1, 1970
- 0
I have a 68030 accelerator card that connects to an optional RAM
expansion card. I'd like to design a compatible larger memory
expansion card. This memory card contains an onboard DRAM memory
controller made by QLogic. I can hopefully reverse engineer the
pinouts for the connectors (two 50-pin header connectors) between the
accelerator card and the RAM expansion card by tracing. I have a
smaller capacity card for comparison.
I'm thinking of using a small FPGA board with SRAM memory, but I'm
open to other ideas. The requirements are:
32-bits wide data
8MB ram.
60-80ns response time
Easy to source components in low quantities in the US
Relatively easy to implement (i'm trying KISS here)
low(er)-cost (no profit potential here)
I'm guessing that the addresses that will appear on the address bus
will be arriving to my replacement memory controller shifted (is the
word mapped?) to some particular range, and that I'll need some type
of lookup table to map those addresses to 0-based address bits on the
memory itself. Right?
Is this plan reasonable? The software that configures the OS for the
memory can be setup to accept 8 megs, so I'm not horribly worried yet
about how the OS-side of things is going to be handled.
Thanks
Keith
expansion card. I'd like to design a compatible larger memory
expansion card. This memory card contains an onboard DRAM memory
controller made by QLogic. I can hopefully reverse engineer the
pinouts for the connectors (two 50-pin header connectors) between the
accelerator card and the RAM expansion card by tracing. I have a
smaller capacity card for comparison.
I'm thinking of using a small FPGA board with SRAM memory, but I'm
open to other ideas. The requirements are:
32-bits wide data
8MB ram.
60-80ns response time
Easy to source components in low quantities in the US
Relatively easy to implement (i'm trying KISS here)
low(er)-cost (no profit potential here)
I'm guessing that the addresses that will appear on the address bus
will be arriving to my replacement memory controller shifted (is the
word mapped?) to some particular range, and that I'll need some type
of lookup table to map those addresses to 0-based address bits on the
memory itself. Right?
Is this plan reasonable? The software that configures the OS for the
memory can be setup to accept 8 megs, so I'm not horribly worried yet
about how the OS-side of things is going to be handled.
Thanks
Keith