dacs, microcontrollers and ground planes

[Hank]

I want to interface a ADS1256 24 bit delta-sigma dac to a atmel mega128
microcontroller. The data sheet for the 1256 recommends:

"It is recommended to use a single ground plane for both the analog and digital
supplies. This ground plane should be shared with the bypass capacitors and
analog conditioning circuits. However, avoid using this ground plane for noisy
digital components such as microprocessors."

Only the SPI serial lines (Din, Dout, Sclk, CS) need to be connected between the
uC and the dac. What would be the best way to arrange these two ground planes
between the dac and the uC?

It is a very cool chip...I was searching for something around 16 bits, but this
8 channel 24 bit device that operates up to 30khz sample rate and has a PGA
really caught my attention. I just want to make sure I don't ruin it with a
crappy layout

Thanks,

Hank

 

[Guy Macon]

I want to interface a ADS1256 24 bit delta-sigma dac to a atmel mega128
microcontroller. The data sheet for the 1256 recommends:

"It is recommended to use a single ground plane for both the analog and digital
supplies. This ground plane should be shared with the bypass capacitors and
analog conditioning circuits. However, avoid using this ground plane for noisy
digital components such as microprocessors."

Only the SPI serial lines (Din, Dout, Sclk, CS) need to be connected between the
uC and the dac. What would be the best way to arrange these two ground planes
between the dac and the uC?

It is a very cool chip...I was searching for something around 16 bits, but this
8 channel 24 bit device that operates up to 30khz sample rate and has a PGA
really caught my attention. I just want to make sure I don't ruin it with a
crappy layout

Check the app notes and see if they have a reference layout using a
uP or uC.

Also, depending on your application, you may be able to deisign
in such a way that no digital lines are changing state during your
ADC sample.

 

[John Larkin]

I want to interface a ADS1256 24 bit delta-sigma dac to a atmel mega128
microcontroller. The data sheet for the 1256 recommends:

"It is recommended to use a single ground plane for both the analog and digital
supplies. This ground plane should be shared with the bypass capacitors and
analog conditioning circuits. However, avoid using this ground plane for noisy
digital components such as microprocessors."

Only the SPI serial lines (Din, Dout, Sclk, CS) need to be connected between the
uC and the dac. What would be the best way to arrange these two ground planes
between the dac and the uC?

It is a very cool chip...I was searching for something around 16 bits, but this
8 channel 24 bit device that operates up to 30khz sample rate and has a PGA
really caught my attention. I just want to make sure I don't ruin it with a
crappy layout

Thanks,

Hank

That's not a dac, it's an ADC!

I'd just ground everything hard to the ground plane of the board (I
assume it's multilayer!) The ADC inputs are differential, so they
truck off to whatever your signal source is, with all due respect for
ground loops and magnetic loop area and stuff like that. Delta-sigmas
are pretty forgiving, especially if you use an integration time that
rejects AC line hum.

This board has eight AD7710s, each fronted by an INA129
instrumentation amp. It also has a 68332 uP and a VME interface, all
sharing a common ground plane on a 6-layer pc board.

http://www.highlandtechnology.com/DSS/V385DS.html

Works fine. The pic is of a prototype, so the board is ugly green. We
usually do blue boards in production.

John

 

[Hank]

That's not a dac, it's an ADC!

I'd just ground everything hard to the ground plane of the board (I
assume it's multilayer!) The ADC inputs are differential, so they
truck off to whatever your signal source is, with all due respect for
ground loops and magnetic loop area and stuff like that. Delta-sigmas
are pretty forgiving, especially if you use an integration time that
rejects AC line hum.

This board has eight AD7710s, each fronted by an INA129
instrumentation amp. It also has a 68332 uP and a VME interface, all
sharing a common ground plane on a 6-layer pc board.

http://www.highlandtechnology.com/DSS/V385DS.html

Works fine. The pic is of a prototype, so the board is ugly green. We
usually do blue boards in production.

John

Uhg, I meant ADC...had dacs on my mind when I posted. Impressive board, btw.

So why do all these companies (atmel, ti/bb) tell you to use separate planes? I
looked at past posts on SED and sure enough everyone seems to recommend just
using one ground plane for everything. Anyone ever mention this to the folks
who write the app notes and data sheets???

Thanks

Hank

 

[John Larkin]

Uhg, I meant ADC...had dacs on my mind when I posted. Impressive board, btw.

So why do all these companies (atmel, ti/bb) tell you to use separate planes? I
looked at past posts on SED and sure enough everyone seems to recommend just
using one ground plane for everything. Anyone ever mention this to the folks
who write the app notes and data sheets???

Thanks

Hank

It seems to me that they consider their part to be the center of the
universe, so they ask for stuff like separate analog/digital grounds
meeting under their chip, and sixteen bypass caps, stuff like that.
Most don't explain how this can be accomplished with even two of their
parts on a board, much less a lot of other stuff.

I've bought a few manufacturer's eval boards lately for really fast
(2-10 GHz) stuff, and they don't split planes.

A lot of appnotes are nonsense. The utility of appnotes is that that's
where they often reveal the bugs. If they say "for optimum operation,
Vcc should come up 2.653 milliseconds before Vdd at temperatures above
13C" or whatever, look out. "Optimum" usually means "might not
explode."

John

 

[Klaus Bahner]

Uhg, I meant ADC...had dacs on my mind when I posted. Impressive board, btw.

So why do all these companies (atmel, ti/bb) tell you to use separate planes? I

They don't! If you read the application notes and the EVM manuals
carefully, you will find a lot of remarks that there is no simple answer
to this question. Furtehrmore on TI's 2004 Precision Data Acquisition
Application seminar they also said that "it depends".

In my experience it depends largely on your application. There is
certainly a difference, whether you want to use the ADC for a single
ended thermocouple with voltages in the uV range or for differential
voltages in the 5V range. It also depends on for how many ENOBs you are
heading. I think there is a difference whether you are heading for 23 or
18 ENOBs from the ADS1256. Not to forget your environment, at the
above seminar the had a nice demonstration of the same circuit but with
two different layouts (both were "reasonable" in my opinion), both
worked very well "most of the time": The difference was what happened
when you switched a cell phone on - one continued with the same high
resolution, the other one's ENOBs decreased by 4-6 bits while the phone
started its network search.

If you are able to place your digital and analog stuff in such a way
that the return currents are not crossing each other then a solid ground
plane is equally good as a split plane design. If the return currents
don't cross each other than this is basically a split plane design.
If there is no natural "split plane" design, I prefer a physical split
plane. For example in a current design I'm working on, also using the
ADS1256, I have also a bunch of reed relays, which in my experience
certainly calls for a split plane design. Another thing which comes to
my mind is that the ATmegas's have very fast (a few nanoseconds
risetime) ports which high current capability. In most situations this
is one of the lovely things about the ATmega, but it caused me also some
headache in conjunction with precision analog stuff.

Just my two cents
Klaus

 

[Bill Sloman]

It seems to me that they consider their part to be the center of the
universe, so they ask for stuff like separate analog/digital grounds
meeting under their chip, and sixteen bypass caps, stuff like that.
Most don't explain how this can be accomplished with even two of their
parts on a board, much less a lot of other stuff.

I've bought a few manufacturer's eval boards lately for really fast
(2-10 GHz) stuff, and they don't split planes.

A lot of appnotes are nonsense. The utility of appnotes is that that's
where they often reveal the bugs. If they say "for optimum operation,
Vcc should come up 2.653 milliseconds before Vdd at temperatures above
13C" or whatever, look out. "Optimum" usually means "might not
explode."

I've had the experience of copying an Analog Devices applcation note
for an A/D converter slavishly, and finding that the reference voltage
buffer circuit oscillated (albeit at a very low amplitude) probably
because my tantalum capacitors had a lower ESR than theirs - an extra
resistor and capacitor on each buffer solved the problem.

One thing that Hank could do would be to put an opto-isolator or two
into the SPI link between the A/D converter and the digital hardware.
This means that no digital current flows through the star point
connecting the analog and digital ground planes, which can make life a
great deal simpler in complicated systems. It isn't a cheap solution -
for that you need a rudimentary pulse transformer with a Schmitt
trigger on the receiving side to reconstruct any DC component of the
serial signal - but it is usually painless.

 

[Ken Smith]

One thing that Hank could do would be to put an opto-isolator or two
into the SPI link between the A/D converter and the digital hardware.

Also going through a single ended to balanced and back to single ended
buffer set will keep the logic currents from flowing away from the ground
point.

 

[Ken Smith]

So why do all these companies (atmel, ti/bb) tell you to use separate
planes? I looked at past posts on SED and sure enough everyone seems to
recommend just using one ground plane for everything.

I don't.

If you are working with ADCs and digital on the same PCB, you are better
off to consider the path the ground and Vcc currents follow and control
what happens. This often means that the ADC section's ground plane is
divided from the digital ground plane at some point. All the logic and
VCC that connect the two must run over the neck of ground plane that hooks
the two together.

No logic current should be allowed to run through the signal or reference
ground of the analog section. This can be done by adding a ground plane
section to another layer and using that as the analog circuit's ground.
In some cases you end up with 3 ground planes over each other. These are:
(1) digital ground, (2) analog signal ground and (3) op-amp supply bypass
ground. The anlog signal ground (2) would be a copper fill on the
component side of the board.

In a mixed anlog / digital board, you often find that the digital part
demands more layers than the anlog part. Smart use of these extra layers
in the anlog section can greatly improve matters.

Ideally, the Vcc conection to the ADC should run through an impedance at
the neck point and be bypassed on both sides. This prevents other logic
signals currents from flowing in the ADC's bypass capacitor.

Ideally the analog input should be differential. Even if it is single
ended, it can be very worthwhile to run the signal and ground from the
transducer's output through a twisted pair to the analog section of the
PCB. On the PCB, the signal ground wire is treated as a differential
input. This reduces the noise effects of the differences in ground
points.

 

[John Larkin]

Also going through a single ended to balanced and back to single ended
buffer set will keep the logic currents from flowing away from the ground
point.


--

Assuming everything's on the same board, using optos or diff
conversion will add a heap of parts "isolating" things just a few
inches apart. Everything will use the same ground and Vcc, so the
whole thing usually reduces into an expensive piece of wire, or maybe
an expensive R-C lowpass filter.

It's surprising how many people think optoisolation is some sort of
magical noise preventer, like using garlic to keep vampires away. If
the grounds are local and common, there's no reason to optoisolate.

I sometimes use source termination (as for, say, a bunch of flash ADCs
feeding an FPGA) to reduce the ground bounce that might result from
driving a lot of digital lines from an ADC. It probably helps.

John

 

[Guy Macon]

Also going through a single ended to balanced and back to single ended
buffer set will keep the logic currents from flowing away from the ground
point.

I had one design where the digital outputs of the uC had a lot of
noise on them which was getting into the ADC. I put in a 74HC
buffer running off of a filtered +5V supply and the noise stopped
at the input to the buffer.

 

[John Larkin]

I had one design where the digital outputs of the uC had a lot of
noise on them which was getting into the ADC. I put in a 74HC
buffer running off of a filtered +5V supply and the noise stopped
at the input to the buffer.

It usually helps the gate the buffer, so the constant flailing of the
data bus isn't always present at the ADC or DAC. The bus data *is*
noise, irrespective of the source of Vcc.

Most dacs - serial or parallel - have a serious amount of
digital-to-analog feedthrough.

John

 

[Hal Murray]

It usually helps the gate the buffer, so the constant flailing of the

data bus isn't always present at the ADC or DAC. The bus data *is*
noise, irrespective of the source of Vcc.

Most dacs - serial or parallel - have a serious amount of
digital-to-analog feedthrough.

Is that feedthrough from the data/clock signals, or from the
digital power supply?

How much do I gain by:
Filtering the digital supply to the ADC chip?
Turning off the serial data/clock?

The chip that started this discussion has a max of 30K
samples/sec. Is that slow enough so that all the normal
digital noise averages out?

 

[Joerg]

Hi John,

Agree with everything except one: Garlic does have benefits. Not for driving away vampires though. When I was in Asia several old folks independently told me that any day in my life where I don't take in any garlic will substantially shorten my life expectancy. Must have been a good point because many over there were in their 80's and had smoked heavily most of their life. They didn't even have back pain or a anything else.

So, I figure garlic ought to be good. I guess Jim Thompson would agree .

Terminations: Gentle AC termination instead of Thevenin also helps a lot with noise. A whole lot.

Regards, Joerg

 

[Ken Smith]

It's surprising how many people think optoisolation is some sort of
magical noise preventer, like using garlic to keep vampires away. If
the grounds are local and common, there's no reason to optoisolate.

Well the garlic works doesn't it. There aren't any vampires around here.
I'm sure many people have needlessly used optos and the same sort of
argument.

I sometimes use source termination (as for, say, a bunch of flash ADCs
feeding an FPGA) to reduce the ground bounce that might result from
driving a lot of digital lines from an ADC. It probably helps.

Depending on the flash it may of it may not. If the latch in the flash is
strobed after everything is decided, the spike on the ground doesn't get
to effect the comparitors. If it is a pipelined ADC, the strobe can line
up with some comparing.

 

[John Larkin]

Is that feedthrough from the data/clock signals, or from the
digital power supply?

With the parts I've worked with, the data and clock made a lot more
noise than the supply, although DACs and ADCs certainly deserve clean
supplies. Whenever possible, I try to wiggle converter pins as little
as possible, because the same piece of silicon is used for the analog
and digital stuff. So, for example, a triggerable ADC should be
triggered, and a timeout used to wait for it to be done before reading
it out, as opposed to polling a "done" bit, which would keep thwacking
the poor thing. Besides, if "done" never comes up, your program hangs!

Delta-sigmas are relative immune to digital noise, but it's still best
not to put them on a shared data bus, especially if you're after 20
bits of data or so.

How much do I gain by:
Filtering the digital supply to the ADC chip?

Some, I guess, might as well.

Turning off the serial data/clock?

A lot, in my experience.

The chip that started this discussion has a max of 30K
samples/sec. Is that slow enough so that all the normal
digital noise averages out?

Donno.

John

 

[John Larkin]

Well the garlic works doesn't it. There aren't any vampires around here.
I'm sure many people have needlessly used optos and the same sort of
argument.



Depending on the flash it may of it may not. If the latch in the flash is
strobed after everything is decided, the spike on the ground doesn't get
to effect the comparitors. If it is a pipelined ADC, the strobe can line
up with some comparing.

The point here - I think - is that the output data pattern changes
every clock, and the chip has to drive 8 to 14 or so data lines, that
means a lot of Vcc and ground current is needed to drive the data
lines, and it appears pretty much like random noise, which can mess up
other samples being taken or processed. Source termination makes the
load on each pin look twice as high as the line impedance, or even
more if you cheat a little. This can (I think) reduce chip substrate
bounce. I say "I think" because I've done it a number of times, and
the boards worked well, but they might have worked OK anyhow.

Sometimes you just do stuff that seems like a good idea, and it works,
so you declare victory and keep doing it. This is called
"superstitious learning". A lot of engineering works this way.

John

 

[Ken Smith]

The point here - I think - is that the output data pattern changes
every clock, and the chip has to drive 8 to 14 or so data lines, that
means a lot of Vcc and ground current is needed to drive the data

ASCII art
Imagine this:


........*...!........!........!........... 1 billion amps
........*...!........!........!...........
........*...!........!........!...........
........*...!....*...!........!...........
........*...!....*...!........!...........
........*...!....*...!........!...........
*******.***!****.***!****.***!*********** <- Icc
............!........!....*...!...........
............!........!........!...........
............!........!........!........... not much current
!
!
! Comparitor decides here.

So long as the impedance of the ground is very low, the spikes on the Icc
don't effect the voltage when the comparitors are deciding. The flashes I
played with way back when tried to make this true.

 

[John Larkin]

ASCII art
Imagine this:


.......*...!........!........!........... 1 billion amps
.......*...!........!........!...........
.......*...!........!........!...........
.......*...!....*...!........!...........
.......*...!....*...!........!...........
.......*...!....*...!........!...........
*******.***!****.***!****.***!*********** <- Icc
...........!........!....*...!...........
...........!........!........!...........
...........!........!........!........... not much current
!
!
! Comparitor decides here.

So long as the impedance of the ground is very low, the spikes on the Icc
don't effect the voltage when the comparitors are deciding. The flashes I
played with way back when tried to make this true.
--

Well, it's hard to quantify. I like source termination for other
reasons, so it's pleasing to think that it improves analog s/n too.

I've definitely seen serious data-bus-line noise induced into SAR
adc's, cured by adding gated buffers in the data lines. And DAC
feedthrough is the nemesis of my otherwise-perfect life.

John

 

[Bill Sloman]

Is that feedthrough from the data/clock signals, or from the
digital power supply?

How much do I gain by:
Filtering the digital supply to the ADC chip?
Turning off the serial data/clock?

The chip that started this discussion has a max of 30K
samples/sec. Is that slow enough so that all the normal
digital noise averages out?

The catch with sigma-delta A/D coverters is that any digital noise
synchronised with the sampling frequency will alias down to a DC
offset. Everything else should average out (if it is isn't big enough
to drive the input channel into non-linearity, which can make it a bad
idea to drive the A/D converter close to either end of its range,
though sigma-delta A/D converters are designed to handle "out of
range" input levels at the sampler -it can be worth the trouble to
find out how much headroom you've got).

Filtering the digital supply to the the A/D converter chip is often
worth the trouble - when I've been in problem-avoidance mode, I've
used a separate linear three terminal regulator to provide the ADC
with its own private digital supply tapped off the analog positive
supply, via a passive filter to block any high frequency noise goig
either way.

As John Larkin says, this route is usually less important that the
path through the digital output pins of the A/D converter but it can
end up as the critical path on your system.

In precision analog design, paranoid anxiety can be a virtue.