J
Jamie Morken
- Jan 1, 1970
- 0
Hi,
I have a small ~1Watt 100kHz ferrite transformer (EP13 core) that
generates three floating ~15VDC supplies for powering the gate drive
circuitry (opto plus fet drivers) for a high voltage 100kHz 3.6kW
Hbridge, and I am having some problems with common mode transients from
the Hbridge switching passing back through the gate drive supply
transformer and into the isolated primary ground. The primary ground
has an FPGA on it that is resetting due to the common mode transients.
The gate drive transformer is setup as a forward topology, with a 5V
primary voltage. I am using 20ns mosfet switching on the Hbridge right
now, I think reducing this switching speed ie. to 100ns will help, but
also I am wondering about putting a common mode choke on the gate drive
transformer primary and secondaries to absorb the common mode
transients, ie. this one:
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=490-1069-1-ND
I measured the gate drive transformer interwinding capacitance and got
these results:
29pF primary to secondary1
16pF primary to secondary2
11pF primary to secondary3
(must be wound furthest from primary as it has lowest capacitance)
I was thinking of switching to a split core bobbin to reduce the
interwinding capacitance and reduce the common mode energy transfer back
into the primary, from looking at the capacitances of the transformer I
am using it looks like it is a single section bobbin with the coils
wound on top of each other.
These transformers are from ICE components, I haven't asked them yet if
they can make the transformer with a split core bobbin.
For the 100kHz Hbridge switching, will these lower frequency transients
also pass through the gate drive transformer, as well as the 20ns/50MHz
switching transients? I know the 20ns transients have a lot more energy
than the 100kHz switching, but I am not sure if a lower frequency common
mode filter would also be required for the 100kHz switching.
Also the "X2Y" caps may be able to filter out some common mode noise:
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=709-1009-2-ND
Also right now my FPGA is on a wirewrap board, so I am hoping that once
I use a proper 4 layer PCB with GND/power planes it will have a lot more
common mode immunity.
Also the Hbridge max voltage is 400VDC, so at 20ns switching that would
be 20kV/us transients for the fet switching, and 40V/us transients for
the base 100kHz Hbridge switching.
Any other techniques or suggestions reducing the common mode noise on
the FPGA supply from this Hbridge?
cheers,
Jamie
I have a small ~1Watt 100kHz ferrite transformer (EP13 core) that
generates three floating ~15VDC supplies for powering the gate drive
circuitry (opto plus fet drivers) for a high voltage 100kHz 3.6kW
Hbridge, and I am having some problems with common mode transients from
the Hbridge switching passing back through the gate drive supply
transformer and into the isolated primary ground. The primary ground
has an FPGA on it that is resetting due to the common mode transients.
The gate drive transformer is setup as a forward topology, with a 5V
primary voltage. I am using 20ns mosfet switching on the Hbridge right
now, I think reducing this switching speed ie. to 100ns will help, but
also I am wondering about putting a common mode choke on the gate drive
transformer primary and secondaries to absorb the common mode
transients, ie. this one:
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=490-1069-1-ND
I measured the gate drive transformer interwinding capacitance and got
these results:
29pF primary to secondary1
16pF primary to secondary2
11pF primary to secondary3
(must be wound furthest from primary as it has lowest capacitance)
I was thinking of switching to a split core bobbin to reduce the
interwinding capacitance and reduce the common mode energy transfer back
into the primary, from looking at the capacitances of the transformer I
am using it looks like it is a single section bobbin with the coils
wound on top of each other.
These transformers are from ICE components, I haven't asked them yet if
they can make the transformer with a split core bobbin.
For the 100kHz Hbridge switching, will these lower frequency transients
also pass through the gate drive transformer, as well as the 20ns/50MHz
switching transients? I know the 20ns transients have a lot more energy
than the 100kHz switching, but I am not sure if a lower frequency common
mode filter would also be required for the 100kHz switching.
Also the "X2Y" caps may be able to filter out some common mode noise:
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=709-1009-2-ND
Also right now my FPGA is on a wirewrap board, so I am hoping that once
I use a proper 4 layer PCB with GND/power planes it will have a lot more
common mode immunity.
Also the Hbridge max voltage is 400VDC, so at 20ns switching that would
be 20kV/us transients for the fet switching, and 40V/us transients for
the base 100kHz Hbridge switching.
Any other techniques or suggestions reducing the common mode noise on
the FPGA supply from this Hbridge?
cheers,
Jamie