Capacitance value for PIC crystal

[P E Schoen]

For most of my projects I use either a 14.7456 MHz crystal (57600*256) or
20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using specifies
a 20 pF parallel load, but my boards have 12 pF capacitors. I just noticed
this and I think the value had been selected for a previous brand of
crystal, but the oscillator frequencies measure pretty close to the ideal
value, as follows for five boards:

Board 1: 20.00258 +0.013% 130PPM
Board 2: 20.00039 +0.002% 20PPM
Board 3: 20.00068 +0.003% 30PPM
Board 4: 20.00085 +0.004% 40PPM
Board 5: 20.00073 +0.004% 40PPM

My specification is 0.02%, or 200 PPM, so all are within spec, but perhaps
with the 20 pF capacitors the frequency will be much closer and variation
will be positive and negative. But the application notes I found seem a bit
confusing as to the correct way to figure the load capacitance:

http://www.statek.com/pdf/tn33.pdf
http://www.foxonline.com/pdfs/xtaldesignnotes.pdf
http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm

It seems that the capacitance is determined by:

CL = (CL1*CL2)/(CL1+CL2)+CS

Where CL1 and CL2 are the load capacitors and CS is the stray capacitance,
generally figured about 5 pF. So with my 12 pF capacitors the actual CL = 11
pF and with 20 pF capacitors CL = 15 pF and with 47 pF capacitors (as I
think I used at one time), CL = 28.5 pF. The ideal value appears to be 30
pF. I don't know the actual stray capacitance, but it is a double sided
board with 0805 SMT capacitors and a PIC18F4455 microcontroller in a TQFP-44
package. It has a value of 15 pF or the OSC2 pin but this is characterized
for external clock drive into OSC1.

I think the 12 pF capacitors are OK but I think I will try changing to 20 pF
and see if the frequency comes in closer. The crystal itself is rated 30 PPM
and 100 PPM over the temperature range. Except for board #1, I'm just about
there.

But the CL formula seems a bit strange. Usually, when I see product over
sum, its square root is taken, as for parallel resistors. And if one of the
capacitors is zero, the other apparently has no effect, and that just seems
wrong.

Paul

 

[John S]

For most of my projects I use either a 14.7456 MHz crystal (57600*256)
or 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using
specifies a 20 pF parallel load, but my boards have 12 pF capacitors. I
just noticed this and I think the value had been selected for a previous
brand of crystal, but the oscillator frequencies measure pretty close to
the ideal value, as follows for five boards:

Board 1: 20.00258 +0.013% 130PPM
Board 2: 20.00039 +0.002% 20PPM
Board 3: 20.00068 +0.003% 30PPM
Board 4: 20.00085 +0.004% 40PPM
Board 5: 20.00073 +0.004% 40PPM

My specification is 0.02%, or 200 PPM, so all are within spec, but
perhaps with the 20 pF capacitors the frequency will be much closer and
variation will be positive and negative. But the application notes I
found seem a bit confusing as to the correct way to figure the load
capacitance:

http://www.statek.com/pdf/tn33.pdf
http://www.foxonline.com/pdfs/xtaldesignnotes.pdf
http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm

It seems that the capacitance is determined by:

CL = (CL1*CL2)/(CL1+CL2)+CS

Where CL1 and CL2 are the load capacitors and CS is the stray
capacitance, generally figured about 5 pF. So with my 12 pF capacitors
the actual CL = 11 pF and with 20 pF capacitors CL = 15 pF and with 47
pF capacitors (as I think I used at one time), CL = 28.5 pF. The ideal
value appears to be 30 pF. I don't know the actual stray capacitance,
but it is a double sided board with 0805 SMT capacitors and a PIC18F4455
microcontroller in a TQFP-44 package. It has a value of 15 pF or the
OSC2 pin but this is characterized for external clock drive into OSC1.

I think the 12 pF capacitors are OK but I think I will try changing to
20 pF and see if the frequency comes in closer. The crystal itself is
rated 30 PPM and 100 PPM over the temperature range. Except for board
#1, I'm just about there.

But the CL formula seems a bit strange. Usually, when I see product over
sum, its square root is taken, as for parallel resistors. And if one of
the capacitors is zero, the other apparently has no effect, and that
just seems wrong.

Paul

The parallel resistor equation does not use a square root.

The equation you have is for series capacitors, Paul. That's what the
crystal sees.

John S

 

[P E Schoen]

"John S" wrote in message

The parallel resistor equation does not use a square root.

Du-oh! I was thinking of the formula for impedance (or RMS from AC and DC
components).

The equation you have is for series capacitors, Paul. That's what the
crystal sees.

Hmm. So it's like an LC tank circuit with the crystal acting as an
inductance? OK, yes, that is shown in the equivalent circuit of the Fox
application note.

So, it looks like 30 pF capacitors may be just about right if the stray
capacitance is 5 pF, but if it's 15 pF as noted in the Microchip spec, then
the 12 pF may be just about right. Since it seems that I need to drop the
frequency just a tad, maybe the 20 pF will be spot on. This may be a case
where trial and error methods are needed.

Thanks,

Paul

 

[Jamie]

"John S" wrote in message


Du-oh! I was thinking of the formula for impedance (or RMS from AC and
DC components).



Hmm. So it's like an LC tank circuit with the crystal acting as an
inductance? OK, yes, that is shown in the equivalent circuit of the Fox
application note.

So, it looks like 30 pF capacitors may be just about right if the stray
capacitance is 5 pF, but if it's 15 pF as noted in the Microchip spec,
then the 12 pF may be just about right. Since it seems that I need to
drop the frequency just a tad, maybe the 20 pF will be spot on. This may
be a case where trial and error methods are needed.

Thanks,

Paul

If you're trying to be that critical, wouldn't a trimmer work best?

I have some very small ceramic based types that live happy with surface
mount constraints.

Jamie

 

[rickman]

If you're trying to be that critical, wouldn't a trimmer work best?

I have some very small ceramic based types that live happy with surface
mount constraints.

He's not trying to trim each board, he's trying to get the optimal
capacitance to optimize the variations. The two capacitors are
connected to ground. The crystal sees this as two capacitors in series
since it only sees what is connected to it's pins. So the caps are in
series.

The crystal itself is a mechanically resonant device modeled as a
complex LC circuit with both a parallel and a series capacitance along
with some damping. Check out a few Xtal maker's web pages, there is
usually a document explaining how they work. The external capacitance
adds to the equivalent capacitance of the Xtal. They are typically
designed to work with the specified amount of external capacitance
across their pins.

BTW, 20 pF in series with 20 pF is 10 pF plus the 5 pF stray gives 15 pF
which you say is the amount specified by the Xtal maker. Is that not right?

 

[Martin Riddle]

For most of my projects I use either a 14.7456 MHz crystal (57600*256)
or 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using
specifies a 20 pF parallel load, but my boards have 12 pF capacitors.
I just noticed this and I think the value had been selected for a
previous brand of crystal, but the oscillator frequencies measure
pretty close to the ideal value, as follows for five boards:

Board 1: 20.00258 +0.013% 130PPM
Board 2: 20.00039 +0.002% 20PPM
Board 3: 20.00068 +0.003% 30PPM
Board 4: 20.00085 +0.004% 40PPM
Board 5: 20.00073 +0.004% 40PPM

My specification is 0.02%, or 200 PPM, so all are within spec, but
perhaps with the 20 pF capacitors the frequency will be much closer
and variation will be positive and negative. But the application notes
I found seem a bit confusing as to the correct way to figure the load
capacitance:

http://www.statek.com/pdf/tn33.pdf
http://www.foxonline.com/pdfs/xtaldesignnotes.pdf
http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm

It seems that the capacitance is determined by:

CL = (CL1*CL2)/(CL1+CL2)+CS

Where CL1 and CL2 are the load capacitors and CS is the stray
capacitance, generally figured about 5 pF. So with my 12 pF capacitors
the actual CL = 11 pF and with 20 pF capacitors CL = 15 pF and with 47
pF capacitors (as I think I used at one time), CL = 28.5 pF. The ideal
value appears to be 30 pF. I don't know the actual stray capacitance,
but it is a double sided board with 0805 SMT capacitors and a
PIC18F4455 microcontroller in a TQFP-44 package. It has a value of 15
pF or the OSC2 pin but this is characterized for external clock drive
into OSC1.

I think the 12 pF capacitors are OK but I think I will try changing to
20 pF and see if the frequency comes in closer. The crystal itself is
rated 30 PPM and 100 PPM over the temperature range. Except for board
#1, I'm just about there.

But the CL formula seems a bit strange. Usually, when I see product
over sum, its square root is taken, as for parallel resistors. And if
one of the capacitors is zero, the other apparently has no effect, and
that just seems wrong.

Paul

See appnote 949

<http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf>

Cheers

 

[Robert Baer]

in message

Du-oh! I was thinking of the formula for impedance (or RMS from AC and
DC components).


Hmm. So it's like an LC tank circuit with the crystal acting as an
inductance? OK, yes, that is shown in the equivalent circuit of the Fox
application note.

So, it looks like 30 pF capacitors may be just about right if the stray
capacitance is 5 pF, but if it's 15 pF as noted in the Microchip spec,
then the 12 pF may be just about right. Since it seems that I need to
drop the frequency just a tad, maybe the 20 pF will be spot on. This may
be a case where trial and error methods are needed.

Thanks,

Paul

I used two 18pf (one on each side of xtal to gnd).

 

[Robert Baer]

See appnote 949

<http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf>

Cheers

Does NOT give any "spec" or useful value; very good on hand-waving, tho.

 

[Martin Riddle]

Does NOT give any "spec" or useful value; very good on hand-waving,
tho.

Really, computer problems again?



Cheers

 

[P E Schoen]

"Martin Riddle" wrote in message

Really, computer problems again?

The app note is marginally useful, but I think the easiest method is to
start with something like 18-22 pF capacitors and measure the clock
frequency directly (or better, via a separate pin derived from the clock).
At least that's what I plan to do. YMMV.

At least I found that the load capacitance value given by the manufacturer
is NOT the recommended value for the two capacitors to ground, although it's
a reasonable starting point and probably OK for most purposes.

Thanks,

Paul

 

[Robert Baer]

Really, computer problems again?



Cheers

Stupid!
Read the PDF, i dare you.

 

[Robert Baer]

in message


The app note is marginally useful, but I think the easiest method is to
start with something like 18-22 pF capacitors and measure the clock
frequency directly (or better, via a separate pin derived from the
clock). At least that's what I plan to do. YMMV.

At least I found that the load capacitance value given by the
manufacturer is NOT the recommended value for the two capacitors to
ground, although it's a reasonable starting point and probably OK for
most purposes.

Thanks,

Paul

EXACTLY!

 

[Spehro Pefhany]

It's just Cs = 1/(1/C1 + 1/C2) = C1*C2/(C1+C2) series capacitance.

Does NOT give any "spec" or useful value; very good on hand-waving, tho.

For equal caps, multiply by two and subtract 5pF, round to the nearest
5% or 10% value and you'll be close enough for a microcontroller
clock xtal.

Eg. 17pF->34pF-5pF = 29pF. I'd use 27pF.

Sometimes start-up is enhanced by using different values for the load
caps, haven't had to do that for a while (mostly because the micros
and such like tend to have PLLs and/or dividers in them that allow
the use of crystals in the ~4MHz-25MHz range regardless of what
frequency is actually required).

 

[[email protected]]

For most of my projects I use either a 14.7456 MHz crystal (57600*256) or

20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using specifies

a 20 pF parallel load, but my boards have 12 pF capacitors. I just noticed

this and I think the value had been selected for a previous brand of

crystal, but the oscillator frequencies measure pretty close to the ideal

value, as follows for five boards:



Board 1: 20.00258 +0.013% 130PPM

Board 2: 20.00039 +0.002% 20PPM

Board 3: 20.00068 +0.003% 30PPM

Board 4: 20.00085 +0.004% 40PPM

Board 5: 20.00073 +0.004% 40PPM



My specification is 0.02%, or 200 PPM, so all are within spec, but perhaps

with the 20 pF capacitors the frequency will be much closer and variation

will be positive and negative. But the application notes I found seem a bit

confusing as to the correct way to figure the load capacitance:



http://www.statek.com/pdf/tn33.pdf

http://www.foxonline.com/pdfs/xtaldesignnotes.pdf

http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm



It seems that the capacitance is determined by:



CL = (CL1*CL2)/(CL1+CL2)+CS



Where CL1 and CL2 are the load capacitors and CS is the stray capacitance,

generally figured about 5 pF. So with my 12 pF capacitors the actual CL = 11

pF and with 20 pF capacitors CL = 15 pF and with 47 pF capacitors (as I

think I used at one time), CL = 28.5 pF. The ideal value appears to be 30

pF. I don't know the actual stray capacitance, but it is a double sided

board with 0805 SMT capacitors and a PIC18F4455 microcontroller in a TQFP-44

package. It has a value of 15 pF or the OSC2 pin but this is characterized

for external clock drive into OSC1.



I think the 12 pF capacitors are OK but I think I will try changing to 20pF

and see if the frequency comes in closer. The crystal itself is rated 30 PPM

and 100 PPM over the temperature range. Except for board #1, I'm just about

there.



But the CL formula seems a bit strange. Usually, when I see product over

sum, its square root is taken, as for parallel resistors. And if one of the

capacitors is zero, the other apparently has no effect, and that just seems

wrong.



Paul

Doesn't that thing use the Pierce topology where you have the PIC buffer output driving a 90o phase shift RC that also limits the crystal power dissipation as well as attenuates spurious oscillation modes, then the specified crystal capacitance is on the PIC buffer input to GND. Usually the 90o phase shift C is like more than 10x the crystal C and can be neglected. Also, the actual C used for the crystal accounts for the PIC buffer input capacitance ( is that 3-7 pF range?). Board stray is parallel to all this and adds to the physical crystal capacitors. Maybe use a trimmer on a test board and measure its setting when you hit the magic number. I'm pretty sure you'renot going to get standard capacitors to within 0.02% .

 

[John Devereux]

(fixed useless double spacing of lines )

Doesn't that thing use the Pierce topology where you have the PIC
buffer output driving a 90o phase shift RC that also limits the
crystal power dissipation as well as attenuates spurious oscillation
modes, then the specified crystal capacitance is on the PIC buffer
input to GND. Usually the 90o phase shift C is like more than 10x the
crystal C and can be neglected. Also, the actual C used for the
crystal accounts for the PIC buffer input capacitance ( is that 3-7 pF
range?). Board stray is parallel to all this and adds to the physical
crystal capacitors. Maybe use a trimmer on a test board and measure
its setting when you hit the magic number. I'm pretty sure you're not
going to get standard capacitors to within 0.02% .

He said 0.02% for the final frequency, not the capacitance tolerance!

 

[P E Schoen]

Fred Bloggs wrote in message

Doesn't that thing use the Pierce topology where you have the PIC buffer
output driving a 90o phase shift RC that also limits the crystal power
dissipation as well as attenuates spurious oscillation modes, then the
specified crystal capacitance is on the PIC buffer input to GND. Usually
the 90o phase shift C is like more than 10x the crystal C and can be
neglected. Also, the actual C used for the crystal accounts for the PIC
buffer input capacitance ( is that 3-7 pF range?). Board stray is parallel
to all this and adds to the physical crystal capacitors. Maybe use a
trimmer on a test board and measure its setting when you hit the magic
number. I'm pretty sure you're not going to get standard capacitors to
within 0.02% .

Yes, it uses a Pierce oscillator:
http://en.wikipedia.org/wiki/Pierce_oscillator

The value of the capacitors has relatively little effect on the frequency,
so a change from the 12 pF I have in the circuit now, to 27 pF (more than 2x
the value, and probably close to ideal), will most likely change the
frequency from an average of 20.00066 (boards 2-5) to the exact value of
20.00000, which is a change of 0.0033% or 33 PPM. So the usual 5% capacitor
tolerance will have no measureable effect on the frequency.

It does appear that the proper point on the curve for specified parallel
resonance is on a fairly steep slope, where a change of 10 pF can have as
much as 200 PPM of frequency shift. From 50 pF to 100 pF the shift is only
about 100 PPM, and flattens out at higher capacitor values, probably as it
approaches series resonance. The "pullability" as stated by Fox is expressed
in PPM/pF by:

S = (C1 * 1000000) / (2 * Ct^2) where Ct is sum of Co + CL.

Thus for the specified CL of 20 pF and Co of 20 pF and C1 of 27 pF this is
8400 PPM/pF but this does not seem right.

The design note for Statek gives

TS = C1 / (2 * (C0+CL)^2) which is 0.0084. If that is percent, then it would
be 84 PPM/pF which still seems high. However, I don't really know the value
of C0. The app note further states that disregard for the trim capacitors
may result in errors as much as 0.1%, or 1000 PPM, and for capacitance range
of 100 pF this is more like 10 PPM/pF, which seems reasonable and is
supported by the published curves. Perhaps C0 is much higher than 20 pF?

Paul

 

[John Devereux]

I am missing a temperature spec in all this.
When I tried to calibrate my little PIC frequency counter against a Rubidium standard by adding caps,
I found that a few degrees Celsius temperature change makes a lot of difference.
Zero tc caps may help, trimmers are useful as others pointed out.

Caps that value are usually "zero TC" anyway aren't they? (COG). I think
it's probably more the TC of the crystal itself.

 

[P E Schoen]

"Mike Perkins" wrote in message

If its a genuine AT cut crystal then I would have hoped for a quite good
performance for just a small temperature change.

http://cfm.citizen.co.jp/english/product/cvo_character.html

The ECS crystals I'm using are 100 PPM over -40 to +85 C, with initial
tolerance of 30 PPM. Not bad for less than a dollar:
http://www.mouser.com/ds/2/122/hc-49usx-dn-16344.pdf

You can get them with as little as 10 PPM tolerance and stability, for about
$3 each:
http://www.mouser.com/ds/2/122/ecx-32-6206.pdf

And these are impressive for about $0.40:
http://www.mouser.com/ProductDetail...=sGAEpiMZZMsBj6bBr9Q9aWDZfF25lWfiUcdswAjCEnw=

Paul

 

[[email protected]]

Fred Bloggs wrote in message

















Yes, it uses a Pierce oscillator:

http://en.wikipedia.org/wiki/Pierce_oscillator



The value of the capacitors has relatively little effect on the frequency,

so a change from the 12 pF I have in the circuit now, to 27 pF (more than2x

the value, and probably close to ideal), will most likely change the

frequency from an average of 20.00066 (boards 2-5) to the exact value of

20.00000, which is a change of 0.0033% or 33 PPM. So the usual 5% capacitor

tolerance will have no measureable effect on the frequency.



It does appear that the proper point on the curve for specified parallel

resonance is on a fairly steep slope, where a change of 10 pF can have as

much as 200 PPM of frequency shift. From 50 pF to 100 pF the shift is only

about 100 PPM, and flattens out at higher capacitor values, probably as it

approaches series resonance. The "pullability" as stated by Fox is expressed

in PPM/pF by:



S = (C1 * 1000000) / (2 * Ct^2) where Ct is sum of Co + CL.



Thus for the specified CL of 20 pF and Co of 20 pF and C1 of 27 pF this is

8400 PPM/pF but this does not seem right.



The design note for Statek gives



TS = C1 / (2 * (C0+CL)^2) which is 0.0084. If that is percent, then it would

be 84 PPM/pF which still seems high. However, I don't really know the value

of C0. The app note further states that disregard for the trim capacitors

may result in errors as much as 0.1%, or 1000 PPM, and for capacitance range

of 100 pF this is more like 10 PPM/pF, which seems reasonable and is

supported by the published curves. Perhaps C0 is much higher than 20 pF?



Paul

Another consideration is the phase delay introduced by the gates internal to the PIC. If these are running at say 10ns, that is 10/50 x 360=72o in addition to the 180o inversion. The Pierce allows for 90o from the crystal and points forward, so with the additional 72o, that leaves just 18o shift from the crystal. As the PIC gate Tpd moves around with temperature ( a minuscule amount), so does the phase shift across the crystal, and so does the loop frequency. If you model the crystal as series LC , all paralleled withload C, with assumed Q and look at phase versus delta-f/fo, that is chnagein phase as a function of ratio of frequency perturbation to resonant frequency ( the most popular plot), that will give an idea of how the oscillator loop frequency pulls with its phase shift.
I think Co in that manufacturer's pulling equation is also called header capacitance, or the net capacitance between the metalization of the crystal and the conductive housing.

 

[[email protected]]

[email protected] writes:






(fixed useless double spacing of lines )
















He said 0.02% for the final frequency, not the capacitance tolerance!



--



John Devereux

Right , IIRC the frequency shift relative capacitance shift is desensitized by sqrt(Q)- not going to do a bunch of algebra right now.