Hi all,
I have a few questions that I wonder if you could help me with.
1. If a electric MIC has an output impedance of 2.2K, does that mean anything I connect to it must have an input impedance greater than 2.2k?
2. I need the MIC output to be coupled then to an opamp, the value of the capacitive reactance is given by 1/(2*3.142*freq*c). I need to amplify signals in the 2-3khz range. If I use this in the equation and select a value of C, am I looking for the reactance to be 0R or close to this?
3. If I have a 4 layer PCB, with components on both sides of the board is SMD on one side and through hole on the other, what advantage would a 6 layer PCB give?
4. I am using a shift register with Master clear as active low. Normally I would tie this to VDD via a 10K pull up. However, if I wanted this to be configurable by software, ie software to pull this signal low, would I still use the 10K pull up and then a FET to drive this signal low. The FET having a resistor between gate and source to prevent false triggering and then connected to an IO pin of a micro? I am not sure how to calculate the resistor to drive the gate, can anybody help. Note this will be a logic level FET.
Thanks for your help
Raj
I have a few questions that I wonder if you could help me with.
1. If a electric MIC has an output impedance of 2.2K, does that mean anything I connect to it must have an input impedance greater than 2.2k?
2. I need the MIC output to be coupled then to an opamp, the value of the capacitive reactance is given by 1/(2*3.142*freq*c). I need to amplify signals in the 2-3khz range. If I use this in the equation and select a value of C, am I looking for the reactance to be 0R or close to this?
3. If I have a 4 layer PCB, with components on both sides of the board is SMD on one side and through hole on the other, what advantage would a 6 layer PCB give?
4. I am using a shift register with Master clear as active low. Normally I would tie this to VDD via a 10K pull up. However, if I wanted this to be configurable by software, ie software to pull this signal low, would I still use the 10K pull up and then a FET to drive this signal low. The FET having a resistor between gate and source to prevent false triggering and then connected to an IO pin of a micro? I am not sure how to calculate the resistor to drive the gate, can anybody help. Note this will be a logic level FET.
Thanks for your help
Raj
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