# 60 Hz line frequecy divided to 1 pps

Discussion in 'General Electronics Chat' started by signalman72, Oct 9, 2017.

1. ### signalman72

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Hi all. I have built a clock circuit that uses 4017 decade IC's to divied the line frequency down to a usable clock pulse. Basically, one 4017 divides by six and another divides by ten rendering 1 Hz. Then a chain of 4017's go on to perform the counting function. My question is this, what, other than slow alternators would account for a slow clock? I could see that noise may introduce rogue pulses and make a clok fast, but the only thing I would account for a slow clock would be a slightly underspeed line frequency.

At any rate, I have sort of kept an eye on the frequency with my oscilloscope (which has a frequency function) and my observations tend to agree with the slow alternator theory. I am measuring from the 10 Hz portion of the circuit. I see constant fluctuations. A lot of the time, I see a perfect 10, other times I frequently see 9.983 and sometimes 10.02.

I did a little research and found that there is a strict frequency standard that must be kept by all (at least North America) power generation facilities. Apparently, each day the alternators and gear must be adjusted to compensate for any underspeed/overspeed situations that may effect timimg functions. After a couple of days, my clock has lagged the computer clock I have it synched with by nearly four seconds. I figured to see an up and down slight fluctuation over a day or so, with it averaging back out, but so far, it's just running slower.

I will go ahead and post the schematic here. I have made a few changes. I am using a 6/0/6 stepdown transformer. I then rectify the 12 volts with a bridge and then onto a 9 volt linear regulator. I am also using a seperate power supply I built to deliver the HV to the display. Those are pretty much the only modifications I've done, the dividing and counting part of the circuit has not changed.

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Last edited: Oct 9, 2017
signalman72, Oct 9, 2017

2. ### signalman72

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signalman72, Oct 9, 2017
AnalogKid likes this.

3. ### Cannonball

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Hello.

This looks to me like your counter and the power company are very close and probably are within tolerance.
You may need to check with the bureau of standards. The power company has to reach a certain tolerance reading within a 24 hour period.

Cannonball, Oct 9, 2017
4. ### AnalogKid

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It looks like the 4013 is a non-inverting buffer. Why?

Also, its input is triggered by AC line positive peaks, while the electronics power supply GND is referenced to the AC line negative peaks. Are you relying on the 4013's input stage protection diodes to clip the input AC? 70-80 uA is not much current, but still ...

ak

AnalogKid, Oct 9, 2017
5. ### AnalogKid

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AnalogKid, Oct 9, 2017
6. ### signalman72

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@ AK, I guess I never thought about the why or how of the 4013, I just figured it was a pulse shaping stage.

signalman72, Oct 9, 2017
7. ### signalman72

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If I lived in one of their prescribed locations, I'd probably sign up for one of their FDR's!

signalman72, Oct 9, 2017
8. ### dorke

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If your goal is to make an "accurate clock" ,you are on the wrong path.
Use a crystal oscillator, not the line frequency.

Commercial clocks use the 32.768KHz crystal which is very common and dirt cheap,
add an osc. and divider IC like the 4060 or 4521 etc.
Note that there are Single IC clock circuits as well.

dorke, Oct 9, 2017
9. ### signalman72

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You are correct that there are many other ways to derive an accurate time keeper. I have some of those watch crystals! At any rate though, I kind of like the novelty of this circuit and it should be an accurate time base per regulation.

signalman72, Oct 9, 2017
10. ### AnalogKid

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your response makes me wonder - is this your own design, or did you get it from somewhere?

The 4013 is doing pulse shaping, but the 4017 has a Schmitt trigger clock input, so it can do its own cleanup.

Of much more concern is the apparent 160 V amplitude of the clock signal. Any thoughts on that?

ak

AnalogKid, Oct 9, 2017
11. ### signalman72

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Not my design. Found somewhere on the net. I liked the fact that it used 4017 as I had some on hand. Obviously a european designer. I couldnt use the initial line input in the USA and didn't want line voltage on my version of it anyway. I guess the shaping stage could be deleted?

signalman72, Oct 9, 2017
12. ### kellys_eye

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Here in the UK the standard line frequency is 50Hz guaranteed to gawd-knows-what accuracy but over a specific time interval only.

In other words the accuracy can vary at any specific instance but over a specified time interval the errors must cancel out to ensure the overall stated accuracy. Don't know (or care) whether this interval is 1 hour, 1 day or a week etc but the fact that they are allowed to vary the frequency at any one instant in time means your measurements could well be 'accurate' as you see them.

The line frequency is a function of the load on the grid which of course varies over the day (peak times etc). We can monitor the line frequency (thus load) via the following website:

http://www.gridwatch.templar.co.uk/

although it's not allowed (supposed) to fall outside certain limits - whereby the grid could 'throw a wobbly' and chuck some generation stations off line!

kellys_eye, Oct 9, 2017
13. ### AnalogKid

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Even better than the US link above.

* * * *

ak

AnalogKid, Oct 9, 2017
14. ### signalman72

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Nice!

On a somewhat anectdotal note, I set my kitchen stove clock (digital LED readout) with my cell phone early this morning. I suspect it uses line frequency for a base because there is no memory and everytime the power flickers, it must be reset. When I tried to sychronize it with my phone, it ended up being about a second ahead of the phone. Fast forwrd to this afternoon and it is a good heavy second behind. This pretty much cements my idea that the power company is cheating me, lol!

At any rate, I thought they had to clean up the discrepancies every 24 hour period. Either this is not the case, or my service provider is out of it's calibration, or they think "close enough is good enough". Waiting to see when and if the correction happens. Let the synchronous shenanigans begin!

signalman72, Oct 9, 2017
15. ### AnalogKid

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This is not the case. Your "service provider" has nothing to do with line frequency. That is set at the power generating stations, which could be 1000 miles away. Also, AC power is created and delivered over a multiply-redundant grid of interconnections, so at any moment your power could come from a combination of power plants.

ak

AnalogKid, Oct 9, 2017
16. ### signalman72

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@AK, my service provider owns (or at least used to) the generation facilities. Maybe they don't anymore. I get what you are saying though.

signalman72, Oct 9, 2017
17. ### signalman72

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In case anyone is interested, the clock has slowly come around to being 2.5 seconds fast now. It's been interesting observing the swing.

signalman72, Oct 11, 2017
18. ### signalman72

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Since there are so many good knowledgeable folks here....

I have a question about this clock. It is a 24 hour clock. If you look at the schematic I posted, you'll see in the final two counting stages (IC 8&9) the way it is connected to do the count. IC 8 repeatedly counts 0-9 twice and then 0-3 once successively as it goes through its routine. Pin 10 (digit 4) is connected to the resets of both IC 8 and 9 throught the 10k resister and 1n cap. Then of course, pin 4 of IC 9 is connected to the 100p cap and then VCC. There is also the diode between the resets of both and the 100p cap. IC 9 of course repeatedly counts 0-2.

My question is, what exactly is going on there? How are the resistor, caps and the diode in the final two stages causing the IC's to count like that?

Last edited: Oct 12, 2017
signalman72, Oct 12, 2017
19. ### dorke

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It is obviously intended to be a 24 hour clock.
A glance at the circuit diagram reveals that:
The left most Nixie has both the 1 and 2 digits connected.

All that "mambo jumbo r-c-d" have to do with detecting the "23" hours clock state,
after which the next state should be "00" hours.
This is done by activating the RST line of both IC8 and IC9.

"Active" lines in the reset mechanism are: digit 2 of IC9 and digit 4 of IC8.
Note that if digit 2 of IC9 is low (count of IC9 is either "0" or "1") the RST lines of IC8 and IC9 is forced low via the diode(i.e no reset).
Thus on count "14" we have no reset!

When we get to "2x"( x=0,1,2,3) the RST line is no longer forced at low since pin 4("2" digit) of IC9 is "high",the diode is not conducting.
When we get to "24" count pin 10(digit "4") of IC8 is at high causing for a "short" time period the RST pins of IC8 and IC9 to be "high"(via R=10k) reseting the count to "00" (IC8 and IC9 RST).

The 1n cap parallel to the 10k is there to cause a "wide enough" reset high signal.

In general,
I wouldn't use this design,it is cumbersome,very large,costly,not accurate etc.
Why would you want to use it is beyond me.

Hope this helps.

Last edited: Oct 12, 2017
dorke, Oct 12, 2017

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