Processors and memory are made using a ‘process,’ or a foundational form factor in which a chip is fashioned. Over time, these processes have become increasingly compact. While fabricators designed earlier chips using a 14nm process, successive offerings have slimmed down to 10nm, and even 7nm. Despite objections from Moore’s Law, leading fabricators like TSMC are prototyping miniscule 5nm chips for 2020 production. These components pack impressive performance into a miniature package.
These size reductions don’t happen easily. Transistor density is key to reducing chip size; TSMC, Intel, Qualcomm, and others pour research efforts into reducing transistor size accordingly. This is absolutely critical when cramming more transistors into smaller chipsets. The more gateways a chip has, the more operations it can perform in tandem. These smaller transistors also require much less power, rendering newer processes more efficient and capable.
Image credit: WCCFTech.
The Challenges of Compact Chip Designs
We know why compact memory units and SoCs are so desirable. However, these improvements are making quality control increasingly difficult. The rise of FinFET design has made chips intricate. The smaller the surface, the harder it is to scrutinize. Resultantly, surface imperfections shrink in unison. These are harder to detect by optical inspection systems, which compare scanned chip images to stored schematics. In these cases, we need optical systems with improved power and clarity. Unfortunately, these systems have limited optical resolutions. 3D NAND is also tougher to inspect optically, due to high-contrast channel designs and overall surface structure.
Furthermore, newer FinFET designs introduce new variables that fabricators must account for. The stacking and bonding of thin wafers introduces risk into each production step, as these wafer layers are fragile. According to Lam Research, the structure of these chips is tricky to produce. Each chip has a sacrificial structure with spacers, which facilitates fin formation. In the latter stages of production, these extra materials are etched away, creating the final fin structure.
Examining the structures and production issues associated with FinFET design. Image credit: MDPI.
These etchers must be precise and calibrated properly, lest they leave excess material behind. Leftover bonding residue is removed, but necessary tools can damage exposed surfaces. Lastly, Lam states that voids can form more easily as chip size decreases, since narrower gate designs are finicky. These imperfections can adversely affect performance and yield rates.
Optical Inspection and E-Beam Inspection
The two predominant methods currently available, optical and e-beam inspection, help ensure quality control. We’ve touched previously on optical inspection; these systems rely on facility databases, which contain chip diagrams and pictures. Machines scan each chip following production, comparing the image captured against its archives. If the units match, they’re approved. If blemishes are present, afflicted chips are rejected.
Optical machinery uses tools like color examination, magnification, illumination, die sorting, and sidewall inspection to ensure manufacturing parameters are met. Each system looks for obvious defects and minutiae. These can include cracks, dust, fibers, and other stray particles. Both contamination and damage can cause problems over a component’s lifespan.
By comparison, e-beam technology is newer and uses a focused beam of electrons to inspect a chip’s surfaces. E-beams can create detailed etchings, correcting minute flaws in post production. Since these beams can inspect resist layers and scan row by row, they can detect the smallest and deepest imperfections.
An automated optical inspection device goes to work. Image credit: AIA Vision Online.
By a wide margin, optical inspection is faster than e-beam inspection. This difference has been so pronounced in the past, that fabricators only used e-beams for prototyping. Today, optical systems are geared towards high-volume yields. Since e-beam systems generally incorporate one electron beam, they’re inherently slower. This drawback has fueled research into future multibeam systems. Engineers are raising valid concerns regarding multi-beam systems, however, since multiple electron sources can interfere with one another inadvertently.
That’s not to say fabricators must choose one or the other. These technologies are complementary, and each has a place in design and quality control. Because each system is adept at uncovering certain faults, pairing them provides a comprehensive solution. E-beam systems can’t overtake optical systems yet, though their appeal is undeniable – especially in low-yield production. These beams are much more useful for inspecting smaller nodes, which companies are now creating. This engineering trend will incentivize future e-beam investment.
A third technology is emerging to handle inspection at smaller process sizes. Extreme ultraviolet lithography (EUV) is an optical technology, which excels at detecting defects at 7nm and beyond. As this technology evolves, it will overcome many of the shortcomings associated with optical inspection. Furthermore, EUV is effective as a wafer inspection tool, and can find mask defects stemming from wafer-layer printing.
Manufacturing Costs and Future Forecasting
Fabricating thousands of chips in short order is extremely expensive. Chip production incurs billions in R&D, prototyping, and manufacturing costs. With this comes upkeep of manufacturing equipment, and continued investment in new technology. When yield rates suffer due to poor QC, companies waste numerous resources. This cost inflates at scale.
Defect detection is central to limiting superfluous production runs, and cutting down on waste. Optical and e-beam systems are essential investments. That said, e-beam systems tend to be hampered by their expense. Science Direct claims a single e-beam lithography system (commonly referred to as EBL) can cost over $1M, with accessories costing over $100,000 in some instances. Due to their slower speeds and lower-yield application, e-beam systems are relatively inefficient when utilized improperly.
Meanwhile, automated optical inspection (AOI) systems can range in cost from $25,000 to $300,000. Foundries can secure Inline systems in Europe for €70,000. These are much cheaper than their e-beam counterparts, though viability does suffer at small process sizes. Systems incorporating EUV technology come at a higher premium.
For now, EUV and e-beam systems hold the most promise at the smallest process sizes, while optical excels at high-yield defect detection. Depending on technologies like FinFET or MOSFET, some chip manufacturers may favor certain systems. This much is certain: no technology is perfect. Ideally, fabricators will closely marry their processes and inspection methods to minimize defects.