A silicon testbed by integrating Arm’s processing architecture with a unique wafer configuration. This layout paves the way for numerous, concurrent data connections. That connection density pays large dividends for a variety of applications.
For example, machine-learning applications rely on the rapid transmission of large data quantities. Though memory is emerging as the new bottleneck in this process, the processor plays a key role in enabling concurrent operations.
Despite advancements in processing performance, these operations aren’t yet instantaneous. GlobalFoundries and Arm are working to minimize latency within processor cores. These signal paths are crucial, yet they’re subject to the longest delays.
The newest 3D test chip aims to shorten these paths and form dense links between ICs.
The Name’s Bond, Wafer Bond
GlobalFoundries and Arm have employed an improved face-to-face wafer bonding solution.
This system is comprised of two wafers conjoined at their interconnect layers. Through silicon vias (TSVs) are present in one wafer layer which extends into the silicon. These form bumps and aid in revealing connections. This allows the 3D chip to connect to its associated package. These chips are capable of making roughly one million 3D connections per square millimeter. Not only that, these signal paths are now folded as opposed to elongated. That reduces data transmission distances, boosting performance accordingly. Bonding sites are a mere 10 micrometers, distributed across a 300mm wafer. For the 3D chip design to succeed, these wafers must be precisely aligned.
A diagram of face-to-face wafer configuration. Image courtesy of IEEE Spectrum.
This wafer design enables a harmonious pairing between GlobalFoundries’ 12nm FinFET process and Arm’s mesh interconnect technology. Both companies claim this partnership delivers low latency and increased bandwidth in core designs. These benefits extend to mobile processors.
Development Process and Future Applications
The chip’s development has been the result of a 3D Design-for-Test (DFT) initiative, which is focused on scaling the 12nm FinFET process. Testing has largely been successful, leading to increased optimism regarding future viability. Furthermore, both companies pledge to use the 3D chip as a proof of concept for continuing research. GlobalFoundries face-to-face wafer technology will be a springboard for future innovations, especially those involving logic and memory integration. In the eyes of Arm and GlobalFoundries, we’ve only seen the tip of the iceberg.
We’ve mentioned how machine learning will benefit from 3D chip integration, but those same benefits extend to artificial intelligence applications. AI is growing increasingly capable yet complex; these programs will demand more from SoCs as time progresses. Big data will also reap these performance-based rewards.
Arm and GlobalFoundries also emphasize the technology’s potential to facilitate seamless cloud computing. While these software solutions rely on powerful hardware, this 3D experimentation will pave the way for diverse hardware pairings in a plethora of devices.
The unique packaging offered by this emerging technology also promises to reduce costs while boosting yields. Engineering teams will enjoy faster lead times, moving from inception to scaled production in record time.