Having started his career as a design engineer for Wang Computers, it was after around four years that Ted Marena found his energetic personality was well suited to more outgoing positions, and eventually took on field applications engineering before later finding a new niche in sales management.
This then led to a more marketing-based background for Marena, and it was whilst he was working as a director of outbound marketing for Microsemi’s SOC and FPGA business unit that he and his department started to look at a RISC-V (pronounced ‘risk-5’) workshop for customer solutions.
Having been galvanised by the energy and enthusiasm involved in those behind the hardware platform, Marena considered the potential of such an open set architecture. “If Linux could work as an open source software environment,” he thought, “why couldn’t an architecture or a processor infrastructure work as well?”
That was in mid-2016. Now, a little over two years later, Ted Marena is both the RISC-V Foundation’s chairman of marketing and director of its very ecosystem. Here’s what he had to say about his career and experience of the revolutionary platform…
Electronics Point: Given your previous positions, how have these taught you and led you to be so involved in RISC-V, and being a champion for it?
Ted Marena: Before I was at Microsemi, I was at Lattice Semiconductor. That was my real first product marketing role: it was interesting because I came from a sales role–I was a sales manager and sales director–and I understood the interfacing side for the customer. Because I was a design engineer before that, I felt I was on the other side of the table, where I was being promoted and sold to. I understood the designer's perspective; I understood the sales person's perspective.
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When I came into this marketing role, I understood what marketing needed to be delivered because I had been the recipient of it. I was really able to learn from some folks who had been doing marketing for a number of years, most of their career in fact.
These guys gave me a lot of really interesting tools, but I was able to take it to the next level because not only was I taking those basic table stakes of product positioning and the promotion and so on, but I made it my own, too. I feel like this is something that has made me successful, as I made it much more digestible for not only the salespeople but also ultimately for the end customer.
EP: And how would you describe RISC-V as a platform to an engineer or someone who is completely unfamiliar with it? How would you maybe sell it to them?
TM: ‘RISC-V is not a processor architecture’, is the first thing that I would say. It's an open instruct set architecture. In very, very basic terms, a processor has to execute these commands, and RISC-V is a very small set of instructions. The fact is that it has to execute very few instructions for the entire process: if you do all the base instructions plus the extensions, there are less than 200, and so it's a very simple architecture.
The other key benefit here is that the instruction set is frozen. This means that any software that you develop, either as a software firm or engineer, is going to run on RISC-V core forever. These are some of the things that makes it very different. It's a simple architecture: it's open and it is frozen so it can be relied on for a long time to come. This is why a lot of organisations are adopting RISC-V for their processor technology and why board designers [and/or] firmware engineers should be aware of the technology.
Image courtesy of Pixabay.
EP: Got you. For that engineer who is maybe a bit hesitant to adopt RISC-V, what would you say are some of the more gleaming or best-use cases that you could say, “This is really going to help you in the long-run”?
TM: I think that that answer will depend on what type of engineer we're talking with. If you're a chip designer, as an example, there are already a lot of public statements. NVIDIA, for instance, had come out, and they make these big graphics processors and also processors for artificial intelligence and machine learning.
In those SOCs, there's a number of these controllers. They made an announcement, close to two years ago now, that all of those controllers inside of their GPUs were going to be moved to RISC-V. Western Digital made a big announcement in December of last year that every one of their drives–whether it's a flash drive or hard drive–they all have a controller, and all of those controllers are going to be moving to RISC-V. There's a massive amount of momentum to this.
For deeply embedded designers, there's a lot of compelling reasons for RISC-V: you have control over ultimately how you want to have an implementation. That's for the chip designer. For the software engineer or firmware engineer, again, I'd circle back to the fact that the instruction set is frozen. That allows confidence that your investment–in whatever tools you develop and whatever software you develop–is going to run forever. This has actually been a huge challenge because for the existing processor architectures that are out there, every iteration, they keep adding instructions.
Even if you have a product that's three, four years old, all of a sudden you could hear: “Oh, well, if you want to update it, you've got to move to this new architecture. You have to recompile the software”. You have to go through a lot of additional validation and work, and that's something that RISC-V will actually prevent for products that have long lifecycles; or especially, products where there's a certification that you have to go through over and over. RISC-V will really be attractive for a lot of those types of applications.
EP: For you specifically, was there a leading aspect of RISC-V that really drew you in, or was it more of the ‘full package’, as you were saying, given that you have experience with a couple of different hats that interface with it?
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TM: I mean, I can point to what pushed it over the edge for me. Generally speaking, it was all the things we've already talked about. The fact that it's an open instruction set architecture, it's the hardware equivalent of Linux, that's how I look at it. I really liked all the other aspects of it, too. The frozen instruction set, the fact that it's simple, it's clean. The RTL could be inspected if the companies want you to. And just the overall collaboration–all of that was really positive, but what really got me over the edge was at this first conference that I attended.
This was at MIT in July of 2016. It hit me like a ton of bricks. I've been to a lot of conferences, and for most of them, the folks there are older: they just tend to be more senior engineers, architects, folks that are much more experienced and older, I'd say. What was different about this conference is I would say about half the attendees were under 30. It was just a tremendous amount of enthusiasm and interest, and that has actually continued. We've been getting a lot more of the younger generation into the technology, and I just love that. I'm full of energy myself, and it just really connected for me. I’ll just share with you that that was kind of my tipping point.
EP: How do you see RISC-V evolving and becoming a more staple part of every engineer's daily grind?
TM: That's a good question. Just for a brief history, when I started in the marketing role about two years ago, we had 40 member companies at the time. Today, two years later, we have over 100 member companies and it just continues to grow. I mean, almost literally every week we have companies joining. There's also a tremendous amount of interest from China and India. The Indian government has driven for RISC-V to be the standard processor architecture. There's lots of work going on there. There's just massive, really huge interest in China as well. This is globally growing.
Image courtesy of Big Stock.
I think for the desktop engineer, what is going to happen is they will start to see, especially as we get into the second half of next year, a lot of organisations beginning to announce devices. And so there are a few devices that are out today, and there'll be a lot more coming in the back half of 2019 into 2020. It will start to get to a point where the engineers will be able to have a wide selection of RISC-V options from a hardware perspective.
From a software perspective, there is still a lot of ecosystem work that needs to be done. I would say real-time operating systems are actually in very good shape. There's a lot of RTOSs that are already available. Express Logic, for instance, makes a really a popular commercial operating system called ThreadX. Then there's a number of open-source RTOSs like Zephyr and FreeRTOS that are available for RISC-V. So for engineers who need an RTOS, the software's already pretty much there for the vast majority.
It's the Linux development that you're going to see really evolve in the next 18 months, is my prediction. In the next 6 to 12 to 18 months, there'll be a lot of development on the Linux side for RISC-V to make sure that that ecosystem and infrastructure is ready as the chips come to market.
EP: Just from your time working with RISC-V, what are some of the things that you've learned that you've been able to apply to other areas of your career?
Image courtesy of Pixabay.
TM: I would say collaboration. The ability to work with disparate cultures, with disparate people, and being able to utilise data, convince people and generate consensus and move in a direction. I've been able to take some of that learning into my day-to-day work.
EP: Lastly, before an engineer jumps into RISC-V, what would you say is the most important thing for them to keep in mind or learn?
TM: I would say that it's still fairly early on in RISC-V's existence. Today, not everything may be available that's required, but the message that I would leave them with is, “Continue to ask.” There's significant momentum, energy, and amount of money being invested in this technology.
Thank you to Ted Marena for his insight into RISC-V, and we at Electronics Point look forward to seeing the open set architecture go from strength to strength.
For more information on the technology, visit riscv.org.