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Xilinx Coolrunner II CPLD power-down input characteristics?

Discussion in 'Electronic Design' started by Spehro Pefhany, Feb 25, 2007.

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  1. Hi, all:-

    A bit of a long shot here, but does anyone know whether the inputs
    will float on the Xilinx CPLD parts will float when power is not
    applied or do they have a nasty protection structure to a supply pin?

    And if so, what if I float the related Vccio pin-- will that allow the
    input current to be reduced to just leakage current?

    I don't see any info in what appears to be the relevant document:
    http://direct.xilinx.com/bvdocs/appnotes/xapp382.pdf


    Best regards,
    Spehro Pefhany
     
  2. Uwe Bonnes

    Uwe Bonnes Guest

    Some more words are said in the datasheet ds090.pdf, page 11,
    Power-Up Characteristics

    For the protection structure, perhaps check with an ohmmeter/conduction
    tester on an unpowered board...
     
  3. Thanks.

    I would in a NY minute, if I had one..


    Best regards,
    Spehro Pefhany
     
  4. Ken Smith

    Ken Smith Guest

    I can't say for sure about the 3.3V version of the Coolrunner but I do
    know that there was no diode to the Vdd rail on the 5V parts. They seemed
    to have zener/thick-oxide like protection. The input didn't hit a hard
    limit as it passed Vcc+0.7 as a diode would. This doesn't mean your idea
    will work however. The input leakage current may rise quite a bit before
    the hard limit is hit.
     
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