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Working of processor loadable down counter

Discussion in 'Electronic Components' started by JSreeniv, Apr 24, 2009.

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  1. JSreeniv

    JSreeniv Guest

    Hi all,

    i am verifying the 16-bit pulse counter which interfaced with

    I want to know the working of down counter where its values are
    0x0_0000 to 0X3_FFFF

    If am set the time base for 10 us and loaded counter with 1 ms and
    toggling the input pulse_din0 signal at 200 ns than i can calculate
    the number of counts (actual time / time base) = 1 ms/10 us = 1000
    counts...which is loaded into the register CNT_P4P_PC0 which is
    loadable by the processor so now the value in this reg is 0x000003E8,

    1.Now my question is if it decrements to 0 and PC_0 (which is a result
    counter ) incmrements by 1 and the value is laoded to this counter. if
    CNT_P4P_PC0 is not decrements or not equals to 0x0000 than what will
    be the value in both the registers?

    2. second question is how to verify this requirement: The CNT_P4P_PC0
    shall be a processor loadable down counter with a range of a minimum
    of 100 ns to a maximum of 1.3 s.

    please give me some clear will be a great sharing of

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