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Why reset ,generally used is neg edge

I have this question in mind for long time and was able to figure
out .

Generally all flops have active low reset(i think ), resetting is done
on neg edge.
Is there any advantage compared to pos edge reset???
 
J

Joerg

Jan 1, 1970
0
I have this question in mind for long time and was able to figure
out .

Generally all flops have active low reset(i think ), resetting is done
on neg edge.


Reset is usually not edge-sensitive but level-sensitive. IOW the chip is
held in reset state as long as reset is asserted. Also, CD4000 logic
often feature positive level reset.

Is there any advantage compared to pos edge reset???

Negative level has some advantages: If it is bussed you can measure
whether the logic high level is there under normal (operational)
conditions. Makes life easier for the service guys. Issuing a reset can
be done with devices that switch to ground which can save you from
having to run VCC to a remote location (and possibly risking a short).
 
T

Tim Shoppa

Jan 1, 1970
0
I have this question in mind for long time and was able to figure
out .

Generally all flops have active low reset(i think ), resetting is done
on neg edge.
Is there any advantage compared to pos edge reset???

Going back to the late 60's/early 70's, TTL logic had higher noise
immunity in "HIGH" than in "LOW", so clocks and resets and other pulse-
type signals were usually done in the "Active low" scheme to make it
less likely for noise to unintentionally trigger something. "Active
low, passive hi" also had some slight power consumption advantages in
that technology as commonly implemented (hard to believe, conserving
power with straight 7400 TTL!)

Much of the logic we use today uses the same conventions as back then,
even though what we today is almost all CMOS and has about the same
noise immunity in either high or low (I've heard arguments either way
about modern technologies).

Some PMOS and NMOS technologies favored one level over the other but
there's isn't much of that left - is there?

If you look at the original RCA CD4000 CMOS parts, you'll find that
"Active Hi" is most commonly found there. You will find some TTL-type
parts that used "Active Hi" as well.

Tim.
 
J

John Larkin

Jan 1, 1970
0
Going back to the late 60's/early 70's, TTL logic had higher noise
immunity in "HIGH" than in "LOW", so clocks and resets and other pulse-
type signals were usually done in the "Active low" scheme to make it
less likely for noise to unintentionally trigger something. "Active
low, passive hi" also had some slight power consumption advantages in
that technology as commonly implemented (hard to believe, conserving
power with straight 7400 TTL!)

Not to mention that the first TTL gates were mostly NANDs, so
active-low operations and address decodes became the norm. The first
TTL decoders were active low, too, since their output stages were
NANDs.

Most device resets and chip selects are still active low.

John
 
K

krw

Jan 1, 1970
0
Not to mention that the first TTL gates were mostly NANDs, so

The "natural" TTL gate is a NAND.
active-low operations and address decodes became the norm. The first
TTL decoders were active low, too, since their output stages were
NANDs.

Most device resets and chip selects are still active low.

TTL drives more current in the low state so is naturally faster on
the H->L transition. Active low enables take advantage of this
difference.
 
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