I have this question in mind for long time and was able to figure
out .
Generally all flops have active low reset(i think ), resetting is done
on neg edge.
Is there any advantage compared to pos edge reset???
Going back to the late 60's/early 70's, TTL logic had higher noise
immunity in "HIGH" than in "LOW", so clocks and resets and other pulse-
type signals were usually done in the "Active low" scheme to make it
less likely for noise to unintentionally trigger something. "Active
low, passive hi" also had some slight power consumption advantages in
that technology as commonly implemented (hard to believe, conserving
power with straight 7400 TTL!)
Much of the logic we use today uses the same conventions as back then,
even though what we today is almost all CMOS and has about the same
noise immunity in either high or low (I've heard arguments either way
about modern technologies).
Some PMOS and NMOS technologies favored one level over the other but
there's isn't much of that left - is there?
If you look at the original RCA CD4000 CMOS parts, you'll find that
"Active Hi" is most commonly found there. You will find some TTL-type
parts that used "Active Hi" as well.
Tim.