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Why do JFET/FET amps experience the miller effect? There isn't any feedback

Discussion in 'Electronic Design' started by Stephen, Apr 12, 2005.

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  1. Stephen

    Stephen Guest

    Could someone explain why a self biasing JFET amp (for example:\21lb10_1.gif) would
    display the miller effect? There isn't any feedback, so there
    shouldn't be any miller effect.. right?
    of a impedance across a negative gain device."

    In Erno Boberly's great article "JFETS: The New Frontier Part I"
    ( he
    mentions how the JFET amp can have this huge input capacitance with a
    large gain. But.. these amps don't have feedback... so why?


  2. There is a capacitance between the FET drain and gate.
    This arises due to the fact that the gate and channel are
    separated by only a PN junction. That capacitance acts
    as a feedback element. So your premise, "don't have
    feedback", does not apply. (Your conclusions would
    be sensible, otherwise.)
  3. I read in that Stephen <>
    wrote (in <>) about
    'Why do JFET/FET amps experience the miller effect? There isn't any
    feedback', on Tue, 12 Apr 2005:
    There IS feedback, via the drain-gate capacitance. This is analogous to
    the very original Miller effect, due to the anode/plate-control grid
    capacitance in triode valves/tubes.

    Note and admire the bilingual exegesis. (;-)

    If the gate voltage goes down by a small amount, the drain voltage goes
    up by that amount multiplied by the stage gain. So the capacitor demands
    charge as if it had a capacitance larger by a factor equal to the stage
  4. John  Larkin

    John Larkin Guest

    It also arises from the capacitance of the silly plastic breadboard

  5. Stephen

    Stephen Guest

    good point! Thanks to all.
  6. What? ?8-\
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