Why Can't I get This FET To Oscillate

[Watson A.Name - \Watt Sun, the Dark Remover\]

He says "Since a rigorous solution is messy to calculate, we estimate."
In another posting I gave the exact value of 18.3878.

On this same web site an expression is given for the frequency of oscillation as
"f = 1 / (2 * pi * SQRT(6) * R * C). This looks like the expression for a 3 section
phase shift network, not a 4 section network. And the expression is wrong anyway if it is
for a 3 section network. The correct expression is SQRT(6)/(2 * Pi * R * C).

For a 4 section network with all the same Rs and Cs, the expression for the frequency of
oscillation is SQRT(10/7)/(2 * Pi * R * C).

There is a complete solution for the 3 section equal valued network at:

Could you measure the Idss of your MPF102? Short the gate and source together, apply
15 volts to the drain and measure the current. Should be a min of 2 mA and a max of 20
mA. Measure quickly before it heats up. If you only apply 9 volts, Idss will be a little
smaller, but that value will still give us some information about your

particular FET.

At 9V, the original one is 10.5mA but the one I'm using now is about
6.1mA, but as it gets hot it drops rapidly to less than 6. I didn't try
15V, since it'd probably be even worse. Things are getting hot real
fast.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Since you are getting oscillations at such a low frequency, you can just put a 10 meg
resistor in series with the probe tip and measure the ac voltage at gate and drain and
take the ratio. The probe need not be compensated for this

measurement.

I still have a couple problems. I've been watching (Well TV too) this
thing, and after 40 minutes it's damped out again. I changed the bias
resistor, and it takes maybe ten minutes to ramp up, then it osillates
for another 10 or 20 min, then it takes another ten mins to die out. So
even if I take a measurement, it isn't stable enough to be certain the
reading is right. I'm still working on getting the bias right.

But if I put a 10M res in series with the probe, I still have a problem.
The gate resistor is 4.3M, so I've effectively got a parallel
combination that's about 3.1M and as it's barely oscillating w/o the
probe, I would guess it won't osc at all with it. Not to mention it's
still loading down the gate.

I'm thinking it might be better to put a .8M in series with the gate res
to make a 10:1 divider and take the measurement across that res.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Put a *non-electrolytic* capacitor of a few tenths of a microfarad in series with the
10 Meg resistor as well, and then the DC bias won't be upset. And you could use *several*
10 Meg resistors. As long as your scope has enough gain so you can get a useable
indication you should be able to make the measurement.

I don't think you understand what's happening. The JFET's gate has zero
volts bias across the gate resistor, because it's, well, a FET, not a
BJT. And at the freq we're dealing with here, the few tenths of a uF
will be essentially an open.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

What I'm suggesting is a way to measure the gain of your FET when the circuit is
oscillating. The probe with a 10 meg resistor in series with the probe tip would give
about 11 megs DC resistance which would upset your bias when connected

to the gate.

No. There is _no_ voltage drop across the gate resistor because the
gate is essentially an open, the leakage current is literally picoamps.
The cap will not help and is not needed.

So if
you put a 1 uF capacitor in series with the 10 megs and the combination in series with the
probe tip, you will not be upsetting the bias, since there won't be a DC path through the
combination (neglecting the leakage of the cap, which if it is a film cap, will be very
low). I believe your frequency of oscillation is *about* 1 Hz. The impedance of a 1 uF
capacitor at 1 Hz is 159K ohms which is negligible compared to the 10 meg resistor, so you
should be able to get a usable signal to the scope.

Again, the capacitor is of no help. The problem is that the impedance
at the gate is 4.3M, which is so high that if you put a 11M probe on it,
the added attenuation will cause the FET to stop oscillating.

I'm still having problems with maintaining oscillation. But every
change I make takes the better part of an hour to find out. :-(

 

[The Phantom]

to the gate.

No. There is _no_ voltage drop across the gate resistor because the
gate is essentially an open, the leakage current is literally picoamps.
The cap will not help and is not needed.

Just to make sure we're talking about the same thing, is the circuit
under discussion here?


+9V
|
.-.
| |
33k| |
'-'
|
.----------------------------------------------o----o Vout
| |
| o-------o |
.-. | | |
| | | 4.3M .-. |
| | 330k === | | +------o V out
'-' GND | | |
| '-' |
| +|| | |-
o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102
| | | | || |-
| 330k | 330k | 330k | 10u |
| | | | o----.
| | | | | |
| | | | .-. |
--- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | +
--- --- --- --- 3.3k| | --- 2 caps
| | | | See '-' --- 3200uF
| | | | note | | total
=== === === === below === ===
GND GND GND GNF GND GND

I suggested using a cap because I think you do in fact have some DC
bias at the gate. It is possible that you are getting some slight
rectification of the AC on the gate (since it's a junction FET), and
the 10 uF capacitor looks to be an electrolytic (I infer this from the
+ sign on the left plate), and probably has enough leakage to give
some gate bias. I wanted you to measure the gain in the circuit as it
is. I suspect leakage from this electrolytic may be causing some of
your instability problems.

(I just grabbed several 10 uF electrolytic caps, with voltage
ratings from 15 to 63 volts. With 5 volts applied I get around 1 uA
of leakage current. You have a DC path to the 10 uF cap through your
330K resistors, and 1 uA of leakage could raise the voltage across the
4.3 Meg resistor to several volts if it weren't for its tendency to
forward bias the gate of the (junction) FET. And, of course, the
leakage changes slowly with time as you apply voltage to the 10 uF
cap. Then, when the circuit is powered down, the capacitor de-forms,
as it were, and the leakage starts out higher and then decreases again
the next time you power it up.)

This is another disadvantage of the lead form of the phase shift
network that hadn't occurred to me until now. With the lag form, you
would have several smaller caps in series from the drain, with a
resistor at each stage to bleed off the leakage.

If you have a 10 uF film cap handy, you might try putting that in
place of the electrolytic you have there now (I'm assuming it is an
electrolytic now).

Again, the capacitor is of no help. The problem is that the impedance
at the gate is 4.3M, which is so high that if you put a 11M probe on it,
the added attenuation will cause the FET to stop oscillating.

The AC impedance at the gate is essentially equal to the impedance
of the phase shifting network looking back toward the drain. At the
expected frequency of oscillation, .576 Hz, I calculate it to be
223192 ohms. This AC impedance should not be loaded very much by an
11 meg probe. On the other hand, without the 1 uF non-electrolytic
capacitor in series with the probe, I would expect the 11 megs to
change the DC bias which I am sure you have at the gate.

 

[Chuck Harris]

No. There is _no_ voltage drop across the gate resistor because the
gate is essentially an open, the leakage current is literally picoamps.
The cap will not help and is not needed.

Come on Watson, there has to be a signal on the gate. A PSO is an
inverting amplifier with a 180 degree lead/lag network feeding back
output signal to the input.

If you truly have no signal, you have no oscillation.

combination in series with the


DC path through the

Again, the capacitor is of no help. The problem is that the impedance
at the gate is 4.3M, which is so high that if you put a 11M probe on it,
the added attenuation will cause the FET to stop oscillating.

There are two modes of operation going on in this oscillator: The DC biasing
with its feedback stabilization, and the AC signal, with its feedback network.

The DC biasing is caused by the voltage drop in the source resistor.
As the FET tries to draw too much iGD, the voltage drop on Rs increases,
putting the gate more into the cutoff, or OFF, region, which reduces the voltage
drop on Rs, which puts the gate less into the cutoff region, ... Because your
source capacitor is huge, this will be a measurable effect all by itself,
albeit a very damped one, as the bias circuit is a source follower and has a DC
gain that is *always* less than one (so it is always stable).

The AC signal path is the one that has fairly high gain. It must have a gain
of at least 29x for my circuit to work. This is easily measurable, remove your
phase shift network, and stick a capacitor coupled, 100 millivolt signal (any
audio frequency will do) into the gate, and measure the signal on the drain.

For your circuit to operate, you had better see a couple of volts on your drain!

(Conversely, if your oscillator is working, it must have about 100 mv on your
gate.)

Your gain is: Av = -Vo/Vi, we are only interested in AC voltages!


-Chuck Harris

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Just to make sure we're talking about the same thing, is the circuit
under discussion here?


+9V
|
.-.
| |
33k| |
'-'
|
.----------------------------------------------o----o Vout
| |
| o-------o |
.-. | | |
| | | 4.3M .-. |
| | 330k === | | +------o V out
'-' GND | | |
| '-' |
| +|| | |-
o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102
| | | | || |-
| 330k | 330k | 330k | 10u |
| | | | o----.
| | | | | |
| | | | .-. |
--- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | +
--- --- --- --- 1.0k | | --- 2 caps
| | | | See '-' --- 3200uF
| | | | note | | total
=== === === === below === ===
GND GND GND GNF GND GND

The circuit is essentially the same, except that I've changed the source
bias to three Si diodes in series, and a 1k resistor. I think I'll
lower the 1k even lower, to get the bias point to where the sine wave
swings are more symmetrical.

I suggested using a cap because I think you do in fact have some DC
bias at the gate. It is possible that you are getting some slight
rectification of the AC on the gate (since it's a junction FET), and

With the attenuation of the RC netwrok being 18, I don't see how the
signal swing could be more than 9V / 18 or 1/2V peak-to-peak.

the 10 uF capacitor looks to be an electrolytic (I infer this from the
+ sign on the left plate), and probably has enough leakage to give
some gate bias.

I used a larger cap before, and it was leaky, which upset the bias. I
changed it to 10uF, and the leakage problem went away. I'm not saying
that the 10 uF has none, just that it seems that it's much, much less
than the larger cap. As a precaution, I could change it to a different
cap. However I don't have a 10 uF in a non-'lytic that's anything
reasonable in size. I can parallel a few 1 uFs instead. The reactance
of the 10 uF is about 24k at .67Hz. If I go to a 1 uF the reactance
will be 240k, which is more than 5 percent of the 4.3M gate resistor,
and adds appreciably to the attenuation. In this circuit, with its
damped osc problem, that can make the difference between sustained
oscillation and damped.

I wanted you to measure the gain in the circuit as it
is. I suspect leakage from this electrolytic may be causing some of
your instability problems.

Instability? Inability - to sustain oscillations. Before with the
larger leaky cap, I couldn't get the drain more than a half volt above
the source, the leakage was causing the gate to be too 'open' and let
too much current thru the FET. Now, after a half hour, the oscs damp
out and the drain voltage is in the 6 or 7V area, which means that the
FET's gate is doing a good job of 'closing', IOW the neg voltage
(measured between source and gate) is sufficient. This leads me to
conclude that there isn't appreciable leakage into the gate.

(I just grabbed several 10 uF electrolytic caps, with voltage
ratings from 15 to 63 volts. With 5 volts applied I get around 1 uA
of leakage current. You have a DC path to the 10 uF cap through your
330K resistors, and 1 uA of leakage could raise the voltage across the
4.3 Meg resistor to several volts if it weren't for its tendency to
forward bias the gate of the (junction) FET. And, of course, the
leakage changes slowly with time as you apply voltage to the 10 uF
cap. Then, when the circuit is powered down, the capacitor de-forms,
as it were, and the leakage starts out higher and then decreases again
the next time you power it up.)

I put the DMM on .2VDC range across one of the 330k resistors. It
measured under 100mV when I powered on, and after maybe 4 or 5 minutes
it measured under 30mV, when the readings started to fluctuate as it
began oscillating. So choosing the 33mV point, .033V / 330,000 gives
1/10 uA, which when multiplied by 4.3Megs gives .43V, which isn't enough
to upset the bias and is more than the actual value, when the 10uF
finally gets charged up.

This is another disadvantage of the lead form of the phase shift
network that hadn't occurred to me until now. With the lag form, you
would have several smaller caps in series from the drain, with a
resistor at each stage to bleed off the leakage.

I think you got those reversed, above. Lead is CR, lag is RC as in the
schematic above.

For the schematic above, it's a disadvantage because the JFET requires
negative bias, hence DC isolation from the lag network. If it were a
MOPSFET, the above schematic could be an advantage because it would be
self biasing, and the four 330k resistors would be part of the bias
network. IOW it would be simpler than the lead network, requiring less
resistors. But yeah, the lead network would be simpler in this case
with the JFET, and less prone to leakage. I started out with the CR
lead network, but didn't have success maintaining oiscillations. So I
switched, probably on recommendation of others here.

The one thing I like about the CR lead netork as far as BJTs go is that
the waveform is less distorted because it's a low pass filter. Higher
harmonics at the collector get fed back to the base where they are
cancelled.

I think it's been on long enough to stabilize and the oscs are damped
out. BRB. Well, the oscs are almost damped out, and I measure across
one of the 330ks about 1 to 2 mV, which is about .005 uA leakage.
That's less than .02V across the 4.3M bias resistor. But now that it's
damped out and stable, I'll measure the DCV across the 4.3M. BRB.
Well, the meter is still jumping around zero, but as best as I can tell
it's swinging from neg 10mV to pos 11 or 12mV, which seems to agree
somewhat with the leakage estimate. Of course I didn't include the
DMM's resistance, but I think it's 100M on the 200mV range.

I'm convinced that the leakage isn't a prob, and changing the cap isn't
gonna help. What do you say?? Maybe I should try a 10uF tantalum, but
is that gonna be a help?

If you have a 10 uF film cap handy, you might try putting that in
place of the electrolytic you have there now (I'm assuming it is an
electrolytic now).

I would have to use a handful of 1 uFs, but I think I will have a huge
problem with picking up a lot of extraneous noise and hum, since this
huge glob of caps will all be at very high impedance and acting like a
large antenna. :-(

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Come on Watson, there has to be a signal on the gate. A PSO is an
inverting amplifier with a 180 degree lead/lag network feeding back
output signal to the input.

If you truly have no signal, you have no oscillation.

Well, yeah, I have no oscillation after the better part of an hour; it's
finally damped out. :-(

But I should've said no DC voltage. AC voltage, yes, when it's
oscillating, but it's finally... damping... out...

 

[John Woodgate]

I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt
[email protected]>) about 'Why Can't I get This FET To Oscillate', on
Fri, 7 Jan 2005:

If I go to a 1 uF the reactance
will be 240k, which is more than 5 percent of the 4.3M gate resistor,
and adds appreciably to the attenuation. In this circuit, with its
damped osc problem, that can make the difference between sustained
oscillation and damped.

I don't think so. 240 kohms in quadrature with 4.3 Mohm is 4.3066..
Mohms. The attenuation is quite negligible.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt
[email protected]>) about 'Why Can't I get This FET To Oscillate', on
Fri, 7 Jan 2005:

I don't think so. 240 kohms in quadrature with 4.3 Mohm is 4.3066..
Mohms. The attenuation is quite negligible.

Not only is there some attenuation, there is also the phase shift.

 

[John Woodgate]

I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt
[email protected]>) about 'Why Can't I get This FET To Oscillate', on
Fri, 7 Jan 2005:

Not only is there some attenuation, there is also the phase shift.

3.2 degrees.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

That's why I said "slight".


In another posting John pointed out that the reactive and resistive components combine
in quadrature, so that the ratio of 240K to 4.3 Meg doesn't by itself indicate what the
change in gain requirement will be for a change to 1 uF. As you pointed out to him in
response, there is the changed phase shift to consider. One really has to analyze the
full phase shift network. The 10 uF and 4.3 Meg you have there now changes the required
gain also, and I thought I would calculate the numbers for the cases we're talking about.

For a network of 4 equal 330K/1uF sections, the theoritical required gain is -18.3878

For the four sections plus the 10uF/4.3Meg the required gain is -20.0796

For the four sections plus the 10uF/4.3Meg and with 11 Megs additional to ground at the
gate, the required gain is -20.7562

For the four sections plus 1uF/4.3Meg the required gain

is -21.7218, so changing the 10

uF to 1 uF raises the required gain by 21.7218/20.0796, or 8.2%.

And, of course, the frequency of oscillation changes, about +7.7% from the first to
last case described above.

I may put a couple 1 uF mylars in parallel to see if there's any diff,
but I don't think the lower leakage will make any diff.

One thing I found out is that if I put the DMM leads on those high Z
points, it perturbs the oscillations, so if it's oscillating, it tends
to damp out, or if it's damped out, the noise I introduce starts to make
it try to start oscillating again.

You've really piqued my interest now. I can't imagine what would aspect of this
circuit would have a time constant on the order of 1/2 hour!

Well, there's 3200 uF across the source resistor, and the currenmt thru
the FET is only about 100 uA with the 33k drain resistor. The FET
starts out low resistance but as it gets biased it starts to have a
substantial resistance so it slows down the charging of the source byp
cap. It just takes a long time to reach equilibrium. And by that time,
what oscillation it had has then damped out.

[snip]

Well, I guess that eliminates that issue. My capacitors came out of the parts drawers
and hadn't been used for years, if ever. Yours has been getting plenty of power-up use,
and the leakage has gotten comfortably low. Darn.

I made up a jig with a socket for the FETs. I used two 9V batts, one
for the drain supply and the other for the neg bias on the gate. Below
are the values I got for the Vgs(off). The data sheet uses 15V on the
drain, but I used only 9VDC, so it isn't exactly the same, but close.
It was really difficult to get the 100k neg V adjust pot to stay put at
2 nA (which was 2 mV across a 1M rsistor). I measured a total of 26
MPF102s, some Moto's, some Signetics, some not marked with a logo.

MPF102 (26 total measured) Jan 7, 2005
Vgs(off) @ Vds=9V, Id=2nA (2mV across 1M)
(all voltages negative. Datasheet specs use Vds=15V)

3.56, 3.34, 1.90, 3.46, 2.44, 3.69, 3.97, 3.21, 3.58,
3.44, 2.20, 2.96, 2.39, 4.65, 3.47, 4.06, 3.28, 4.02,
3.76, 2.62, 1.92, 2.85, 3.05, 3.14, 3.55, 2.10**

**The 2.10V is the JFET I have been using for the oscillator.

As you can see, altho there was a somewhat wide variation, most of them
were in the 2 to 4V range.

Yes. That's what comes of writing this at 3:00 AM.


But as I pointed out in another post, this also means that you have lots of feedback at
high frequencies. The MPF102 is specified as a VHF amplifier. You could more easily have
parasitic oscillations at some high radio frequency that would upset the operation of the
circuit with the lead topology.

Well, with impedances of megohms and a load resistor of 33k, the
parasitic capacitances make a low pass filter that makes it difficult to
oscillate at those freqs. With BJTs, the usual method is to put a 47 pF
from the collector to base, or an even larger value across the collector
load resistor.

Here's a suggestion. Get rid of the components you have in the source lead now. Make
a small stiff, adjustable bias supply by connecting 3 penlight alkaline cell in series.
Put a 100 ohm (or thereabouts) trimpot across the 4.5 volt battery. Connect the most
negative terminal of the battery to ground, and connect the source of the FET to the wiper
of the trimpot. You will have gotten rid of a big capacitor and possible source of long
time constant behavior, and have an easily adjustable, low impedance

bias supply.

I could just use the 9V supply and a resistor and zener to do that,
instead. Same diff and it saves batteries. ;-) Thanks.

[snip]

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt
[email protected]>) about 'Why Can't I get This FET To Oscillate', on
Fri, 7 Jan 2005:

3.2 degrees.

Yeah. And then that causes the freq to change a bit compensate, etc,
etc.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

But you also have in series with every component, the parasitic inductance of the leads,
especially with a bread board type setup. I can usually tell when there are VHF
oscillations because of the "antenna" effect. You put your hand within an inch of the
circuit and get major changes in behavior. I think you would have noticed if this were
happening. Anyway, you're not using the lead form of the network now.


Again, the leads of the 47 pF cap have inductance, especially when breadboarding where
the leads are left long, and there is a frequency where the cap and its leads are series
resonant. This can *cause* oscillations, rather than suppress them, if the transistor has
a high enough cutoff frequency. I used to think it would be a good idea to have a
transistor with a very high cutoff frequency to use for everything. That way you would
never have to worry if the transistor was fast enough. So I tried using a 2N3866 for
breadboarding; bad mistake. Almost everything you build with a 2N3866 will oscillate if
you use *breadboard* techniques.

Yeah, been there, done that, got the T-shirt! I worked with UHF and
microwave (radars) so I'm wary and wise enough to know when and what to
do to keep things behaving, RF-wise.

I have gotten the impression that your 9V supply is a "transistor radio" type 9V
battery. I was thinking that the 3 penlight cells would have substantially longer life
when providing the proposed low impedance bias supply.

Either a HP 6214 or a Power Designs 2005 precision regulated PS, so I
set it and the DMM reads 9.000.

But at the currents that this osc is using it would be just fine, a 9V
battery should last months at a hundred microamps!

Anyway, I think the variable bias supply and no capacitor would be a good experiment to
try.

Well, I still have to bypass the bias supply, so it'll have almost no
degeneration on the oscillations. I changed from a zener to TL430, and
some pot that will handle a bit of current. I have to get the TL430 in
there somewhere. I'm working on it.

;-) Thanks.

[snip]

 

[The Phantom]

Well, I still have to bypass the bias supply,

You bypassed it with 3200uF before; at .67Hz that's an impedance of
74 ohms. Why do a lot better than that now? If you put a 100 ohm
trimpot across your bias supply with the wiper connected to the source
as I proposed, you would have a maximum of 25 ohms source resistance
(with the trimpot set in the middle; less at any other setting)
without any capacitor, which I think would be a good thing; (the lack
of a capacitor, that is . Getting rid of the capacitor also
eliminates the complication of extra phase shift that John Jardine
discussed.

so it'll have almost no
degeneration on the oscillations. I changed from a zener to TL430, and
some pot that will handle a bit of current. I have to get the TL430 in
there somewhere. I'm working on it.

;-) Thanks.

[snip]

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

With Vgs(off) in this range, your FETs should have

transconductances much higher than

the 2000 minimum. I just can't understand the behavior you're getting (oscillations dying
out). I may have to see if I can find an MPF102 of my own and breadboard this thing.

I hope you can try the fixed source bias idea; I think we could get some good info from
that.

Yeah, I set that up last night. I used a TL431 with a 270 ohm resistor
to 9V, so there's about 25 mA current thru the resistor, and 2.5V across
the '431. Then I put a 200 ohm pot across the '431 and connected the
wiper to the fet's source and the 1000 uF byp cap, and I removed the
2200uF. Something like 12 mA thru the pot.

I now can adjust the source to a somewhat fixed voltage. When I turned
it up to about 1.5V Vs, it started oscillating, then the voltage kept
creeping up to 2V, and the oscs died out. I had to fiddle with it, and
wait a bit for the caps to charge up. When the Vs is at 1.55 to 1.6V,
it seems to stay fairly stable and it's been oscillating all night long.
Yeah, finally! Not fully rail to rail, but stable oscillations. My
guess is that the square law characteristic of JFETs might be the reason
it's limited.

I had three diodes in seires that were giving about the same Vs, along
with the 1k resistor. I didn't reduce the resistor lower, but I think
that if I had used a 470 or maybe lower, it might have stabilized and
not damped out. I may try that later, since this is just an experiment.


-->| o--------o-----/\/\/\---o 9V
|- | | 270
S| | 2.5V o----+
FET | | | |
| / ----/ |
o---->\ / / \---+
/ ----
200 \ | TL431
| |
o--------o
|
===
GND

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

be
a good experiment to

Well, I still have to bypass the bias supply,

You bypassed it with 3200uF before; at .67Hz that's an impedance of
74 ohms. Why do a lot better than that now? If you put a 100 ohm
trimpot across your bias supply with the wiper connected to the source
as I proposed, you would have a maximum of 25 ohms source resistance
(with the trimpot set in the middle; less at any other setting)
without any capacitor, which I think would be a good thing; (the lack
of a capacitor, that is . Getting rid of the capacitor also
eliminates the complication of extra phase shift that John Jardine
discussed.

so it'll have almost no
degeneration on the oscillations. I changed from a zener to TL430, and
some pot that will handle a bit of current. I have to get the TL430 in
there somewhere. I'm working on it.

;-) Thanks.

[snip]

I forgot to include the byp cap in the followup I just posted, so here's
a corrected schem. I reduced it from 3200 to 1000 uF. That's enough as
you say above. It's there, and doesn't do much except help prevent
noise from the rest of the circuit from getting into the source.



-->| o--------o-----/\/\/\---o 9V
|- | | 270
S| | 2.5V o----+
FET | | | |
| / ----/ |
o---->\ / / \---+
| / ----
+| 200 \ | TL431
1000 --- | |
uF --- o--------o
| |
=== ===
GND GND

 

[Tony Williams]

I could just use the 9V supply and a resistor and zener to do
that, instead. Same diff and it saves batteries.

That capacitor *has* to be got rid of. There are other
problems as well though. The low voltage across S-D
is running the jfet in a place where it has a low output
impedance, and lots of distortion. The even-harmonic
components in the distortion is probably accumulating on
the capacitor and shifting the bias point, away from
oscillation.... a sort of leisurely squegging.

If you have to stay with a 9v supply, then a folded cascode
circuit could take away a lot of the fundamental problems.
As below, LTSpice says it works ok.


+--------------------------------------+9V
| |
\ \
/2k /1k5
\ \
_|_ 0.15mA approx, |
\_/ +--<-----------------------------+<--7V
| |/e so Rin= 180 ohms approx. |
+---|pnp | Id= 1.2mA
| |\ | Rd= 5k.
| | R2 R R |--+
| +--/\/\--+--/\/\--+--/\/\--+-->|J1,2N3819
| | 135k | 150k | 150k | |--+
| | +| +| +| |<--4.7V
\ \R1 ===C ===C ===C |
/1k6 /15k | | | +----+
\ \ | | | \_|_ |
| | | | | ZD1/_\ |
| | | | | 4v7 | |
| +--------+--------+--------+------+0V |
| R1=15k, and R1+R2 = R always. |
+-------------------------------------------+

The effective Drain load is R1, but the folded cascode
allows a high jfet current (high gm) and yet at the same
time have a high value of load resistance. The 180 ohm
input resistance at the pnp emitter means that about 90%
of the AC current from the jfet goes down the transistor
and it means that the AC Vd-s voltage is almost zero
(which keeps the distortion low).

The lagging phase-shifter allows a dc-coupled negative
feedback type of self-biassing. The dc voltage across R1
will always be 4.7V minus whatever Vg-s the jfet needs for
an Id of 1.2mA. The gm of the jfet has to be about 2.2mA/V
for the circuit to oscillate.

With the generic 2N3819, LTSpice gives a dc-operating point
of about 2.6V across R1, and an AC oscillation voltage of
4.8V pk-pk. The sinewave looks reasonable, just flat bottoms
at about 0.4V, as the transistor runs out of current.

For the lagging phase shifter, F= root-6/2.pi.R.C and with
1uF caps the simulated frequency is 2.59Hz.

It takes a few hundred seconds for the oscillation to come
up and finally stabilise.

 

[Jim Thompson]

That capacitor *has* to be got rid of. There are other
problems as well though. The low voltage across S-D
is running the jfet in a place where it has a low output
impedance, and lots of distortion. The even-harmonic
components in the distortion is probably accumulating on
the capacitor and shifting the bias point, away from
oscillation.... a sort of leisurely squegging.

If you have to stay with a 9v supply, then a folded cascode
circuit could take away a lot of the fundamental problems.
As below, LTSpice says it works ok.


+--------------------------------------+9V
| |
\ \
/2k /1k5
\ \
_|_ 0.15mA approx, |
\_/ +--<-----------------------------+<--7V
| |/e so Rin= 180 ohms approx. |
+---|pnp | Id= 1.2mA
| |\ | Rd= 5k.
| | R2 R R |--+
| +--/\/\--+--/\/\--+--/\/\--+-->|J1,2N3819
| | 135k | 150k | 150k | |--+
| | +| +| +| |<--4.7V
\ \R1 ===C ===C ===C |
/1k6 /15k | | | +----+
\ \ | | | \_|_ |
| | | | | ZD1/_\ |
| | | | | 4v7 | |
| +--------+--------+--------+------+0V |
| R1=15k, and R1+R2 = R always. |
+-------------------------------------------+

The effective Drain load is R1, but the folded cascode
allows a high jfet current (high gm) and yet at the same
time have a high value of load resistance. The 180 ohm
input resistance at the pnp emitter means that about 90%
of the AC current from the jfet goes down the transistor
and it means that the AC Vd-s voltage is almost zero
(which keeps the distortion low).

The lagging phase-shifter allows a dc-coupled negative
feedback type of self-biassing. The dc voltage across R1
will always be 4.7V minus whatever Vg-s the jfet needs for
an Id of 1.2mA. The gm of the jfet has to be about 2.2mA/V
for the circuit to oscillate.

With the generic 2N3819, LTSpice gives a dc-operating point
of about 2.6V across R1, and an AC oscillation voltage of
4.8V pk-pk. The sinewave looks reasonable, just flat bottoms
at about 0.4V, as the transistor runs out of current.

For the lagging phase shifter, F= root-6/2.pi.R.C and with
1uF caps the simulated frequency is 2.59Hz.

It takes a few hundred seconds for the oscillation to come
up and finally stabilise.

Come on, Tony, you done gone and ruined this whole thread by
introducing some actual engineering thought into the process ;-)

...Jim Thompson

 

[Tony Williams]

Come on, Tony, you done gone and ruined this whole thread by
introducing some actual engineering thought into the process ;-)

Sorry Jim.......

The folded cascode (with dc feedback bias) was my favorite
circuit when using a single jfet, it evades all sorts of
problems. By ratio'ing the currents it is even possible
to do the self-bias for constant gm, as per the Siliconix
app note TA70-2.

In this case, getting 29x off a 9Vdc rail is possible,
but still a little too marginal for comfort.