Why Can't I get This FET To Oscillate

[Watson A.Name - \Watt Sun, the Dark Remover\]

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


--
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[gcd]

Hi,
try increasing Rd. The gain of the cct should be gmRd so you need to check
the typical figure for gm ( 2000 to 7500uS for a 102) and then determine the
correct minimum Rd. Try using a pot.
if gm =2000 then Rd = 14k5
if gm = 7500 then Rd = 3k9

Cheers
Greg

 

[John Larkin]

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.

In addition to the need for gain (and jfets have low gain) the
"lead"-type phase shift network needs to see a low impedance at its
output. A bipolar base provides this low impedance, a fet doesn't. A
lag-type phase shifter is more appropriate for a fet.

But phase-shift oscillators tend to be rotten anyhow.

Hey, this guy has a few really terrible circuits on his web page!

John

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Hi,
try increasing Rd. The gain of the cct should be gmRd so you need to check
the typical figure for gm ( 2000 to 7500uS for a 102) and then determine the
correct minimum Rd. Try using a pot.
if gm =2000 then Rd = 14k5
if gm = 7500 then Rd = 3k9

Cheers
Greg

Thanks. The first JFET I used needed a 1.5k for the source resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but of
course that meant a higher source resistor for more neg V on the gate.
So instead I put a 1N4148 in series with the resistor to give a .6 or so
volt dtop. That helped bring the drain voltage up to closer to half the
9V supply voltage. But it still wouldn't osc, just a damped sine wave.
So I swapped the JFET, and that got it to be a bit better, but still a
damped sine wave. I decided to put another 1000 uF across the source
bypass cap, total 2000, and it helped a bit. So I kept putting more of
them across, and the damped wave kept getting longer. I'm up to 5400
uF, and it will 'ring' for more than a minute but it's still a damped
sine wave. I'm gonna try a higher value drain load, as you suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value. I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is so much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the 'right
one'. Before, I was lucky to find two of them at Rat Shaft, and with my
luck, they'd both be the same. And I wasn't about to go all over town
to buy more and have to spend tens of dollars to do so.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

of


In addition to the need for gain (and jfets have low gain) the
"lead"-type phase shift network needs to see a low impedance at its
output. A bipolar base provides this low impedance, a fet doesn't. A
lag-type phase shifter is more appropriate for a fet.

But phase-shift oscillators tend to be rotten anyhow.

Hey, this guy has a few really terrible circuits on his web page!

You mean Bowden's website? He posts here regularly. Thanks for the
advice. I could always lower the resistors, I suppose. But I may
change it to lag type if I can't get it to behave. See my other
followup.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

the source should be on the resistor side and the drain to the 9volts.
i don't know if that will fix it, also did you make sure you used
a jFet and not a MOSFET?

Thanks. It's a MPF102. The circuit works, but it's a damped sine wave,
it just won't sustain oscillation. After I made several changes (see
other followup), it is taking longer to damp, but still not sustaining
oscillation. I'm working on it, thanks to other's advice.

 

[John Popelish]

Thanks. The first JFET I used needed a 1.5k for the source resistor. I
increased the drain load from 3.9k to 10k, to get more gain, but of
course that meant a higher source resistor for more neg V on the gate.
So instead I put a 1N4148 in series with the resistor to give a .6 or so
volt dtop. That helped bring the drain voltage up to closer to half the
9V supply voltage. But it still wouldn't osc, just a damped sine wave.
So I swapped the JFET, and that got it to be a bit better, but still a
damped sine wave. I decided to put another 1000 uF across the source
bypass cap, total 2000, and it helped a bit. So I kept putting more of
them across, and the damped wave kept getting longer. I'm up to 5400
uF, and it will 'ring' for more than a minute but it's still a damped
sine wave. I'm gonna try a higher value drain load, as you suggest.
But I still have to deal with rebiasing it with a higher source
resistor. I used a pot, but I guess it wasn't high enough value. I'll
tinker with it some more after awhile.

One thing that's always bothered me about JFETs is that there is so much
variance in the gm and Idss from part to part. Now that I have a
bagful, I'm not so concerned with having to swap them to find the 'right
one'. Before, I was lucky to find two of them at Rat Shaft, and with my
luck, they'd both be the same. And I wasn't about to go all over town
to buy more and have to spend tens of dollars to do so.

I would be tempted to put a pair of NPN emitter followers on the
drain, one for the output and one to drive the capacitive line.

 

[Jamie]

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

I used a 1.5k source resistor bypassed by a 1000 uF cap. The drain load
resistor is 3.9k, and the supply voltage is 9VDC. The 3 caps are 10 uF,
and the three resistors to common are 150k each. The FET is a MPF102.
The drain voltage is about half the supply voltage.

When I power it up, I get the damped sine wave, I can see it on the DVM.
The voltage gain for a PSO has to be at least 29 to oscillate, so
apparently I don't have enough V gain to make up for the losses in the
network.

How do I get more V gain out of the single FET? The source is fully
bypassed. Thanks.


--
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###Got a Question about ELECTRONICS? Check HERE First:###
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My email address is whitelisted. *All* email sent to it
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Don't be ripped off by the big book dealers. Go to the URL
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Just when you thought you had all this figured out, the gov't
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the source should be on the resistor side and the drain to the 9volts.
i don't know if that will fix it, also did you make sure you used
a jFet and not a MOSFET?

 

[Rich Grise]

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

Do you mean this one?
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#phase.gif

you link puts me at "Triangle and Squarewave Generator".

If you mean the "Low Frequency Sinewave Generators",

I used a 1.5k source resistor bypassed by a 1000 uF cap.

Well, that'll kinda degenerate your source follower output.

The drain load
resistor is 3.9k, and the supply voltage is 9VDC.

This confuses me, because the circuit I see has no drain load resistor,
it's merely a source follower buffer. The 2N3906 is the gain element.

Or are you talking about a completely different circuit?

Thanks,
Rich

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Do you mean this one?
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#phase.gif

you link puts me at "Triangle and Squarewave Generator".

If you mean the "Low Frequency Sinewave Generators",


Well, that'll kinda degenerate your source follower output.


This confuses me, because the circuit I see has no drain load resistor,
it's merely a source follower buffer. The 2N3906 is the gain element.

Or are you talking about a completely different circuit?

Sorry for any confusion. Yes, the correct link is to the low Freq Gens,
not the func gen. And when I said "I built up a FET version of the
phase shift oscillator", I meant I replaced the 2N3904 with a JFET, but
used the schematic on the right of that link as the starting point. I
haven't got to the point of adding a source or emitter follower yet, I'm
just trying to get it to oscillate, not put out a damped sine wave.
J.P. suggested ading an EF to the output, so I may do that soon. Back
to work.. Thanks.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

I was taught that one of the corrolaries of Murphy's Law is...
"Amplifiers will oscillate. Oscillators won't."

Well, it almost oscillates. Like for a minute or so. But the period of
a cycle was 17 seconds - too long.

So I removed the three 10 uFs and put 2.2 uFs in their place. Now it's
faster, but it's back to damped oscillations that settle down in 20 or
30 seconds. Back to work..

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

I would be tempted to put a pair of NPN emitter followers on the
drain, one for the output and one to drive the capacitive line.

I thing that might be a good idea. But I have a couple theories or
ruminations.

This is a 'lead' network. Three CR sections with the last one directly
driving the gate, which is (nearly) infinite input impedance. Each
section contributes 60 degrees phase shift, but say each one was
contributing 45 degrees. Then the reactance of the caps would equal the
resistance of the resistors, which is 150k. So 60 degrees isn't that
much diff, the tangent of 60 is 1.732, but I forget which way, so either
the cap reactance is 150k * 1.732 or 150k / 1.732 (the former makes more
sense). We're talking about an impedance that's considerably above the
drain resistor (which is 16k for now), and much lower than the input
impedance. So this should allow the FET to be better at oscillating
than a BJT. But it doesn't seem that way, with all the problems I'm
having getting it to do better than poop out after a few cycles.

 

[john jardine]

I built up a FET version of the phase shift oscillator on the right of
http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

Couldn't resist it!. Tried Wien arrangements, then gyrated LCs but the
single FETs and transistors just kept running out of gain.
Don't know whether that FET was the main interest, or just that a L.F. Sine
was wanted but the same circuit using an NPN seems to useably work.
regards
john


+9V
|
.-.
| |
27k| |
'-'
|
.------------------------------------o----o 0.1Hz
| ___ ___ | 4Vpp
| .--|___|--o-|___|-o
| | 1M | 1M |
--- | | |
---10u | --- |
| | 10u--- |
| | | |
| || || | GND |/
o----||---o--||----o---------------| Jelly Bean
| || | || |>
| 10u | 10u |
| | o----.
| | | |
.-. .-. .-. |
| |82k | |100k | | |
| | | | 27k| | ---
'-' '-' '-' ---1000u
| | | |
=== === === ===
GND GND GND GND

(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

in message news:[email protected]... http://ourworld.compuserve.com/homepages/Bill_Bowden/page8.htm#func.gif

Couldn't resist it!. Tried Wien arrangements, then gyrated LCs but the
single FETs and transistors just kept running out of gain.
Don't know whether that FET was the main interest, or just that a L.F. Sine
was wanted but the same circuit using an NPN seems to useably work.
regards
john


+9V
|
.-.
| |
27k| |
'-'
|
.------------------------------------o----o 0.1Hz
| ___ ___ | 4Vpp
| .--|___|--o-|___|-o
| | 1M | 1M |
--- | | |
---10u | --- |
| | 10u--- |
| | | |
| || || | GND |/
o----||---o--||----o---------------| Jelly Bean
| || | || |>
| 10u | 10u |
| | o----.
| | | |
.-. .-. .-. |
| |82k | |100k | | |
| | | | 27k| | ---
'-' '-' '-' ---1000u
| | | |
=== === === ===
GND GND GND GND

(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)

Yeah., thanks. I got a couple of those BJT PSOs laying around. In the
above schem, assuming 10u electrolytics, the polarity is real important.
Plus to the base and collector. I've built several with the 'self bias'
resistor between base and collector. In this case, 2M total is kind of
on the high side, unless the transistor has a very high beta. And that
seems especially true with the 27k emitter resistor. Why do you put
that in there? With self bias, it's not really necessary, just wastes V
swing, in the case of an amp.

The above is a lead CR network, which is what I was using. Last nite I
changed the circuit to a lag RC type. It works even worse.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

in message news:[email protected]...

Bingo. Calculate the phase shift of the third section if it works into an
infinite impedance (JFET input impedance.)

Well, each CR has to be 60 degrees to give the 180 total needed. If
not, then the freq changes to make it so.

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

[snip]

equal
the makes
more above
the into
an

Well, each CR has to be 60 degrees to give the 180 total needed.

Why? Are your three sections identical? According to the schematic you
cited, the R of the last stage is the input R of the active device. As I
understand your posts, you substituted a JFET for the BJT, greatly
increasing the resistance seen by the third capacitor in the phase shift
section. A series RC network, in the limiting case of infinite R, has 0
phase shift. I suspect this is the case with your version of the oscillator,
which requires nearly all the phase shifting to be done in the first two
sections. But, as the phase shift of the RC network approaches 90 degrees,
the attenuation approaches infinity, which means you run out of gain!

Run out of gain? Hrm..

There are three CR sections, each consisting of a 2.2 uF cap from the
drain to the gate. Here's the schem that John J. drew, modified for
the JFET. Each CR section has 150k to ground. This was the final
circuit I had before I replace the CR leading network with an RC lag
netowrk - essentially exch'g the Rs and Cs. So now I have 150ks between
the drain and gate, and 1 uF caps to ground, and this version works
worse than the leading network, it has veryllitle if any ringing. I
noitced that one app note, might've been TI, said that there is less
attenuation with four sections, so I may add a 4th section just for
sh!ts and grins. Right now, it's worthless. And the 1 uF caps are
metal film, and they're too big, I'll have yo find some smaller ones to
allow fitting in the fourth section - maybe go back to 'lytics. Oh,
well.

BTW, I think you meant, 'no amount of gain will overcome the
attenuation.'

+9V
|
.-.
| |
16k| |
'-'
|
.------------------------------------o----o 0.1Hz
| | 4Vpp
| |
| |
--- |
---2.2u +------o V out
| |
| |
| || || |-
o----||---o--||----o-------------->| JFET MPF102
| || | || | |-
| 2.2u | 2.2u | |
| | | o----.
| | | | |
.-. .-. .-. .-. |
| |150k | |150k | | 150k | | |
| | | | | | 3.3k| | --- 2 caps
'-' '-' '-' '-' --- 3200uF
| | | | | total
=== === === === ===
GND GND GND GND GND


(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)

 

[Watson A.Name - \Watt Sun, the Dark Remover\]

Second note. you may want to try a R to ground at the
gate, this will help match the phasing angle and mite
be your problem.

Well, the cap already has the 150k to ground at the gate. See my other
followup with the schematic in ASCII. Thanks.

 

[John Popelish]

[snip]

This is a 'lead' network. Three CR sections with the last one
directly
driving the gate, which is (nearly) infinite input impedance. Each
section contributes 60 degrees phase shift, but say each one was
contributing 45 degrees. Then the reactance of the caps would equal
the
resistance of the resistors, which is 150k. So 60 degrees isn't
that
much diff, the tangent of 60 is 1.732, but I forget which way, so
either
the cap reactance is 150k * 1.732 or 150k / 1.732 (the former makes
more
sense). We're talking about an impedance that's considerably above
the
drain resistor (which is 16k for now), and much lower than the input
impedance.

Bingo. Calculate the phase shift of the third section if it works into
an
infinite impedance (JFET input impedance.)

Well, each CR has to be 60 degrees to give the 180 total needed.

Why? Are your three sections identical? According to the schematic you
cited, the R of the last stage is the input R of the active device. As I
understand your posts, you substituted a JFET for the BJT, greatly
increasing the resistance seen by the third capacitor in the phase shift
section. A series RC network, in the limiting case of infinite R, has 0
phase shift. I suspect this is the case with your version of the oscillator,
which requires nearly all the phase shifting to be done in the first two
sections. But, as the phase shift of the RC network approaches 90 degrees,
the attenuation approaches infinity, which means you run out of gain!

Run out of gain? Hrm..

There are three CR sections, each consisting of a 2.2 uF cap from the
drain to the gate. Here's the schem that John J. drew, modified for
the JFET. Each CR section has 150k to ground. This was the final
circuit I had before I replace the CR leading network with an RC lag
netowrk - essentially exch'g the Rs and Cs. So now I have 150ks between
the drain and gate, and 1 uF caps to ground, and this version works
worse than the leading network, it has veryllitle if any ringing. I
noitced that one app note, might've been TI, said that there is less
attenuation with four sections, so I may add a 4th section just for
sh!ts and grins. Right now, it's worthless. And the 1 uF caps are
metal film, and they're too big, I'll have yo find some smaller ones to
allow fitting in the fourth section - maybe go back to 'lytics. Oh,
well.

BTW, I think you meant, 'no amount of gain will overcome the
attenuation.'

+9V
|
.-.
| |
16k| |
'-'
|
.------------------------------------o----o 0.1Hz
| | 4Vpp
| |
| |
--- |
---2.2u +------o V out
| |
| |
| || || |-
o----||---o--||----o-------------->| JFET MPF102
| || | || | |-
| 2.2u | 2.2u | |
| | | o----.
| | | | |
.-. .-. .-. .-. |
| |150k | |150k | | 150k | | |
| | | | | | 3.3k| | --- 2 caps
'-' '-' '-' '-' --- 3200uF
| | | | | total
=== === === === ===
GND GND GND GND GND

(created by AACircuit v1.28 beta 10/06/04 www.tech-chat.de)

You can get a bit less loss out of the phase shift network if you
stage the impedances. Say, 2.2 uf and 150k for the left one, 1uf and
300k for the second one and .47 uf 680k for the right one.

 

[John Larkin]

You can get a bit less loss out of the phase shift network if you
stage the impedances. Say, 2.2 uf and 150k for the left one, 1uf and
300k for the second one and .47 uf 680k for the right one.

Cool. In the limiting case where each RC doesn't load the one before,
three RCs give 180 degrees shift with a gain of 0.125.

If you did 4 RCs like this, 45 degrees each, gain is 0.25!

Etcetera, I think.

John

 

[Jim Thompson]

Cool. In the limiting case where each RC doesn't load the one before,
three RCs give 180 degrees shift with a gain of 0.125.

If you did 4 RCs like this, 45 degrees each, gain is 0.25!

Etcetera, I think.

John

For the equal RC case:

fo = 2.4464/(2*pi*R*C) and Gmin = 29X (amplification, network "gain"
= 34.579E-03

...Jim Thompson