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Why are there no low pin count FPGAs?

D

dalai lamah

Jan 1, 1970
0
Un bel giorno David L. Jones digitò:
We asked the top three FPGA manufacturers to explain this, and their
general response was that it doesn't really cost them any more to put
on all the extra I/O

Really? The next time, can you ask them why the same FPGA cost a *lot* more
in its maximum pin configuration rather than its minimum pin configuration?

Just to make some examples from Digikey:

XC3S400-4FTG256C price 27.76000
XC3S400-4FGG456C price 48.32000

XC3S1000-4FTG256C price 47.87000
XC3S1000-4FGG456C price 63.79000
XC3S1000-4FGG676C price 87.91000
 
Yeah, but what if you want lots of logic and very few IO pins?
That's probably less common than the reverse, running out of pins. My
designs seem more often constrained by pin count than by internal
resources, unless we bite the bullet and go BGA.

You tried BGA ..?

Seems like a challenge ;)
 
D

David L. Jones

Jan 1, 1970
0
dalai said:
Un bel giorno David L. Jones digitò:


Really? The next time, can you ask them why the same FPGA cost a *lot* more
in its maximum pin configuration rather than its minimum pin configuration?

Just to make some examples from Digikey:

XC3S400-4FTG256C price 27.76000
XC3S400-4FGG456C price 48.32000

XC3S1000-4FTG256C price 47.87000
XC3S1000-4FGG456C price 63.79000
XC3S1000-4FGG676C price 87.91000

It's most likely to be phantom pricing. The cost difference in
manufacturing wouldn't be nearly that large. They charge more because
people expect to pay more...

Dave :)
 
The commercial E1 and ATM VHDL cores we had took up lots of resources,
so we needed the biggest device Altera had at the time, and of course
that only came in a 960pin BGA :-(
Makes quick prototyping a ridiculous exercise!

A quick hack is to solder some wirewrap leads to the bga balls. Should not
become a "forrest" if there's so little pins needed.
 
J

John Larkin

Jan 1, 1970
0
On 04 Jun 2006 11:18:13 GMT,
You tried BGA ..?

Seems like a challenge ;)

It was like the transition from thru-hole to 1206 surface-mounts: it
seemed scairy, but it turned out to be no big deal. You do need 6 or
8-layer boards with 10-12 mil vias and 6 mil traces, but that's not
hard to come by these days. Routing is tricky, but you just puzzle
through it. We initially sent the boards out for assembly but then my
production people said "we can do that" and they did. We've only done
about 50 boards so far, with a 456-ball fpga, and we've had zero
defects. I've heard the claim that bga's are easier to do than
fine-pitch TSOP-type things.

John
 
M

M.Randelzhofer

Jan 1, 1970
0
I agree. Too many boards try to be too much => cost..

Thank you very much for yours and Mike's feedback.
Our next FPGA product will be optimized for higher pin count and lower cost.
But there are still lots of customers who likes 5V cmos levels...

The GOP-XC3S200 module was originally designed for a customer who wanted to
redesign an old video processor board consisting of tens of GAL devices with
an FPGA device.
So level shifters were necessary to fit into the old 5V sockets.
The logic design was easily copied from the old PALASM sources to VHDL.
After certifying the new design with all the old software, a new pcb layout
with an FPGA was done. The customer was happy, because the transtion to the
new technology was fast and simple.

Since there are lots of unused pins on a TQFP100 to DIL24 adapter board, an
SRAM seemed to be the most meaningful extension to our GOP-XC3S200 module.

For lots of FPGA designs, a RAM device is very handy, especially for video
or audio applications. We currently produce some adapterboards with 7
segment led displays, usb and rs485 tranceivers, audio adc's and audio dac's
which fits into the testconnector of our modules.
These are intended to help in studying logic design.
Some application designs will be published to show digital audio potentials
of FPGA's.

MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
 
It was like the transition from thru-hole to 1206 surface-mounts: it
seemed scairy, but it turned out to be no big deal. You do need 6 or
8-layer boards with 10-12 mil vias and 6 mil traces, but that's not
hard to come by these days. Routing is tricky, but you just puzzle
through it. We initially sent the boards out for assembly but then my
production people said "we can do that" and they did. We've only done
about 50 boards so far, with a 456-ball fpga, and we've had zero
defects. I've heard the claim that bga's are easier to do than
fine-pitch TSOP-type things.

Quick thought without looking at chip packages. Maybe bga can "afford" larger
pad area because there's more area underneath the chip than at the
circumference ..?
 
J

John Larkin

Jan 1, 1970
0
On 04 Jun 2006 22:20:46 GMT,
Quick thought without looking at chip packages. Maybe bga can "afford" larger
pad area because there's more area underneath the chip than at the
circumference ..?

Maybe so. And BGA balls are inherently planar, unlike gullwings that
can get offset in handling and not all sit flat on their pads.

Of course, inspection and rework get sorta nasty.

I think I could program an FPGA to inspect all its own solder joints.

John
 
pad area because there's more area underneath the chip than at the
Maybe so. And BGA balls are inherently planar, unlike gullwings that
can get offset in handling and not all sit flat on their pads.
Of course, inspection and rework get sorta nasty.
I think I could program an FPGA to inspect all its own solder joints.

There's another approach to solder bga. Have some kind of bed of nails to which
the bga is soldered onto. If an attachment fails, one just desoldered that
particular nail by the heat from the underside which the nail will conduct.
Or it may simple just reattach by the heat added.
The "nails" could be wires too ofcourse..

BGA
Nail/Wires
----PCB----- <- Holes to allow insertion of "nails".
Solderingside

Just brainstorming ;)
 
K

Keith

Jan 1, 1970
0
On 04 Jun 2006 22:20:46 GMT,


Maybe so. And BGA balls are inherently planar, unlike gullwings that
can get offset in handling and not all sit flat on their pads.

Yes, and self-centering, as well.
Of course, inspection and rework get sorta nasty.

Not so bad. The contractors I've used do X-Ray inspection and have
full rework capability (re-balling BGAs can be expensive, but clost
to the cost of a big FPGA). BGAs haven't been much of an issue for
a decade (and IBM has been doing essentially the same thing with C4
for three).
I think I could program an FPGA to inspect all its own solder joints.

Sure, you could program it to "inspect" for shorts and opens.
Cracks, slight misplacement, and "almost opens" might be a little
more difficult.
 
S

Sproket

Jan 1, 1970
0
Of course, inspection and rework get sorta nasty.

Nasty, no. Expensive, yes if you want it done right.

~750K for an Agilent 5DX X-ray. The rework stations can also range up
to some very expenive propositions. Both of previous require well
trained operators.

Trained operators/programmers is probably more important than the
actual equipment used.
I think I could program an FPGA to inspect all its own solder joints.

John

Unlikely.
The multiple power and ground pins would not be possible. X-Ray is
just about the only way to check those pins.

Depending upon the board design, it can be quite easy to test FPGA
with JTAG. Corelis, Asset-Intertech, Jtag Technologies, Goepel all
make exceedingly well designed JTAG test packages.
 
J

John Larkin

Jan 1, 1970
0
Nasty, no. Expensive, yes if you want it done right.

~750K for an Agilent 5DX X-ray. The rework stations can also range up
to some very expenive propositions. Both of previous require well
trained operators.

Trained operators/programmers is probably more important than the
actual equipment used.

It'd be cheaper for us to throw away the bad boards.

We do have a prism viewer thing that works pretty well 5 or 6 balls in
from the edges, and can catch gross shorts even deeper.
Unlikely.
The multiple power and ground pins would not be possible. X-Ray is
just about the only way to check those pins.

Well, OK, but if it works, enough power and ground pins are likely
connected. I was thinking that one could test all i/o pins for opens
or shorts, without requiring any other part on the board to have JTAG,
which few do in most situations.

John
 
D

dalai lamah

Jan 1, 1970
0
Un bel giorno David L. Jones digitò:
They charge more because
people expect to pay more...

This is a further clue to something I'm aware from a while: there isn't any
real competition in FPGA market. When you can afford to sell different
package options with more than a 100% markup, announce new models that
won't be available for months, don't have any distributor that can handle
to sell small quantities of your bigger models, it means that you run a
monopoly. A and X just pretend to be in competition.

Until some time ago I was very excited about FPGA technology. Now the FPGA
vendors are pushing me away from it. I know it's a pity, but what should I
do?
 
D

dalai lamah

Jan 1, 1970
0
Un bel giorno John Larkin digitò:
We've only done
about 50 boards so far, with a 456-ball fpga, and we've had zero
defects. I've heard the claim that bga's are easier to do than
fine-pitch TSOP-type things.

No one denies that when you are in production stage there isn't any real
problem with BGA. But when you are in prototyping stage, I don't think any
one would try to solder a 100$ BGA with a toaster oven or any other
ridiculous home-made solution that you can read on the Internet...
 
J

John Larkin

Jan 1, 1970
0
Un bel giorno David L. Jones digitò:


This is a further clue to something I'm aware from a while: there isn't any
real competition in FPGA market. When you can afford to sell different
package options with more than a 100% markup, announce new models that
won't be available for months, don't have any distributor that can handle
to sell small quantities of your bigger models, it means that you run a
monopoly. A and X just pretend to be in competition.

Until some time ago I was very excited about FPGA technology. Now the FPGA
vendors are pushing me away from it. I know it's a pity, but what should I
do?

If you don't push the bleeding edges, there are some fantastic deals,
like a Spartan XC3S200-TQ144 for 11 bucks in modest quantities. That's
"200,000 equivalent gates" of ecl-speed logic for 5 millicents per
gate, if you buy the equivalence claim. It helps balance those
GigaComm gates at $35 each.

John
 
J

John Larkin

Jan 1, 1970
0
Un bel giorno John Larkin digitò:


No one denies that when you are in production stage there isn't any real
problem with BGA. But when you are in prototyping stage, I don't think any
one would try to solder a 100$ BGA with a toaster oven or any other
ridiculous home-made solution that you can read on the Internet...

Except that people do!

But the important thing about soldering BGAs reliably is the
time-temperature profile, and you need a decent conveyerized oven and
some ride-through instrumentation for that.

John
 
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