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Why are there no low pin count FPGAs?

Discussion in 'Electronic Design' started by M. Noone, Jun 3, 2006.

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  1. M. Noone

    M. Noone Guest

    Hi - I was considering th possibility of replacing a microcontroller
    (Atmel atmega168) with an FPGA. I realized that an FPGA would be much
    better suited for the application. The only FPGA work I've ever done
    was with the popular Xilinx Spartan3 board. I started looking for a
    suitable replacement chip - and I quickly ran into an issue: all FPGAs
    are huge! A search at digi-key of 'FPGA TQFP' found chips with 100 pins
    and more - nothing less. Such a large chip won't even physically fit on
    this board. So - can anybody explain what I'm missing here? Is it that
    FPGAs are normally designed to run with external memory, so they need a
    large bus for that? I am aware of the smaller BGA FPGAs, but I don't
    have the equipment to produce FPGA boards.


  2. John  Larkin

    John Larkin Guest

    The smaller parts are called CPLD's. They start at 20 pins or so.

  3. Terry Given

    Terry Given Guest

    Yeah, but what if you want lots of logic and very few IO pins?

  4. Tilmann Reh

    Tilmann Reh Guest

    But there also are no "larger" CPLDs in small packages...

    I would have needed them several times. For example, the smallest
    package for the Xilinx 95144XL is the TQFP100 (with 0.5mm pitch :-( ) -
    I would like that chip in a 44-pin package for applications with less I/O.

    The dilemma is, there simply are no such larger programmable logic
    devices (no matter if CPLD or FPGA) in small packages (from neither
    maker). Seems there's not much market to them, or they didn't recognize
    there is one...
  5. Leon

    Leon Guest

    Most customers want lots of I/O, the market for smaller packages would
    be limited and they would be very expensive.

  6. Slurp

    Slurp Guest

    Well your problem here is lots of logic. Lots of logic = large silicon area.
    Large silicon area = large package. Manufacturers are not going to produce a
    18 x 18mm package - or larger - with 20 pins!
    It is just uneconomic to do so.

    If you have a minimal logic requirement go for a CPLD, packages typically
    will have fewer pins.

  7. Guest

    Consider this, is it easier to not use a pin rather than trying to add a pin
    for a customer that needs it?
    FPGA capabilities is a compromise. Otherwise people would just had an asic
    So it makes more business sense to have one chip sold to those that needs many
    pins and those that doesn't need them. Split the production, and cost rises.
    The only argument I can see is that of not useing bga packaging. And too thin
    pitch that is just unsolderable by any normal means.
    And one could always make a small breakoutboard vq100->dil14 etc.. if one wants
  8. Tim Wescott

    Tim Wescott Guest

    Or the chips are huge and _need_ those big packages.

    Although I'm always willing to believe in vendor stupidity.


    Tim Wescott
    Wescott Design Services

    Posting from Google? See

    "Applied Control Theory for Embedded Systems" came out in April.
    See details at
  9. Rich Grise

    Rich Grise Guest

    If you're just talking about board real estate, then with the little teeny
    tiny pins on those little flat packages, the whole thing is about the size
    of a postage stamp. Just lay out your board with the .5mm traces or
    whatever, and strap the unused pins to Vcc or gnd. IOW, figure out the
    mounting, and just ignore the pins you don't need. Then the only problem
    is the PCB layout.

    Good Luck!
  10. John Larkin

    John Larkin Guest

    That's probably less common than the reverse, running out of pins. My
    designs seem more often constrained by pin count than by internal
    resources, unless we bite the bullet and go BGA.

  11. qrk

    qrk Guest

    Virtex 2 has small BGA packages with 0.8mm pin pitch. There are web
    sites discussing how to solder BGA packages at home using a toaster
    oven. Many designs require large amounts of I/O. Thus, the FPGA
    manufacturers cater to the average. Plus, a large percentage of pins
    are power/ground.
  12. M. Noone

    M. Noone Guest

    That seems to be what I was missing. As discussed in this topic by
    others though - these seem to be much more limited in features.

    So that brings me to a new question: Are there any FPGA/CPLD like
    devices that have built in ADCs? That is the only feature of importance
    I'd be losing by switching over to a CPLD from a microcontroller. Does
    such a thing exist? The board that this is intended for is very small
    (1.5x4.725cm) and very full so having to add an external ADC would be

  13. John Larkin

    John Larkin Guest

    You might check Actel. You can also make a single-slope or delta-sigma
    ADC using mostly internal FPGA resources, if accuracy needs are
    moderate. There are also tiny ADCs around, SOT-23 and smaller.

  14. You are right, all FPGA's have HUGE pin counts. The higher the logic
    density the greater the pin count. It is one of my pet hates.
    For one of our applications we needed one of the top of the line FPGA's
    for the density, but only needed about a dozen I/O pins. So we were
    forced to use a *960* pin BGA - INSANE!

    We asked the top three FPGA manufacturers to explain this, and their
    general response was that it doesn't really cost them any more to put
    on all the extra I/O, and there is most demand for the high pin count,
    so they have simply abandoned the low pin count market for good. If I
    recall correctly, Actel were the only ones who put their hand on their
    heart and said they would continue to support the "low-ish" pin count
    QFP packages.

    Dave :)
  15. John Larkin

    John Larkin Guest

    Wow, what sort of application needs all those gates but only a dozen

  16. Counters.
  17. John Larkin

    John Larkin Guest

    Cool. If we use SPI to manage and read out the counters, that leaves 9
    count-input pins. So you can have nine, say, 10,000 bit counters.

  18. It was a dual path redundant E1 data stream over 155Mbit ATM fibre. So
    basically, just 6 serial buses in and out - a dozen pins total plus a
    few misc.

    The commercial E1 and ATM VHDL cores we had took up lots of resources,
    so we needed the biggest device Altera had at the time, and of course
    that only came in a 960pin BGA :-(

    Makes quick prototyping a ridiculous exercise!

    Dave :)
  19. We produce small FPGA and CPLD boards in a PAL compatible 24pin DIL pinout.
    The FPGA board also incorporates 512kx8 SRAM and 8Mx1 FLASH.
    It's well suited for education purposes and serial I/O.


    However lots of customers asks for more I/O's...

    So the next ones have more I/O's, for $++.


    PS: ROHS forces us to sell out our PB contaminated modules, so its prices
    are very userfiendly...

    Michael Randelzhofer
    FPGA und CPLD Mini Module
    Klein aber oho !
  20. A 40 pin DIL option would be nice, also maybe a basic lower-cost version without flash, sram and
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