Micropower bandgaps show up in really mundane areas of chip design
nowadays, such as POR. Really overkill, but because customers know it
can be done, they expect it to be done. If you reverse engineer Maxim
chips, you'll find a bandgap comparator circuit in the POR. Plenty of
patents on such circuits, but never litigated to my knowledge. They do
save power since the bandgap and comparator are folded into one
circuit.
Yes, on chips this is no problem but no company has marketed those
individually at a decent price. Meaning the sub-10uA references are
usually not very suitable for mass production because you can't have a
reference in there that costs more than all the rest of the board. So we
have to use tricks such as pulsing and storing.
One reason why POR/BOR circuits contain precise references is that the
chips they are on need it elsewhere as well. For example, a uC with an
ADC on board. The often touted "cheat reference" consisting of four
equal resistors hung onto the rail doesn't cut the mustard.
One of the trickier micropower circuits are those in thermal shutdown.
That is where leakage can really kill you, so parasitics are required.
However, it isn't exactly rocket science.
BTW, I forgot to mention it, but UCLA has a fair amount of analog
design classes. Lastly, there is the Swiss Federal Institute of
Technology (or close to that). They have all sorts of papers on
dynamic biasing scheme, i.e. schemes to make micropower op amps slew
quickly by boosting tail current, etc.
We didn't have much luck with UCLA so far. They didn't understand my
module specs and couldn't even solder. Had to let them go. Europe would
be an option but the immigration procedure is a real hassle. Plus there
will be an expensive international move required unless you catch them
right after their degree. Europe doesn't have such an extreme shortage
of analog guys because larger companies there are often foolish. Some of
them consider anyone over 40 a geezer that needs to be replaced by a
kid. The consequences are very visible, for example with NXP's web site.
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POR really should reflect what it takes to make the chip fly, not
necessarily some arbitrary specification. That is, logic needs at
least a VT, the worse case of N or P. So generally a chip POR will
have a circuit that insures you at least have enough juice to turn on
your worse case fet. Once you trust the logic (well, at least under
static conditions), the next step is to insure the bandgap is awake,
generally an output something above a VTN. Throw in a timer and
hysteresis to make sure the supply rail hasn't sagged. Stuff like
that. Thus POR is process and temperature dependent. However, as you
probably know, that doesn't give the customer the warm and fuzzy
feeling. They want to see something nice and snappy that can be
verified with a DVM.
[/QUOTE]
The customer won't even be able to hold a DVM to it if on-chip. What
customers like me really want to see is a POR plus BOR where brown-outs
are handled properly. Anything less than that is a risk. For some reason
it usually takes the uC folks years to figure that out, no idea what
they find so difficult about it.
