Which chip familly for 100Mhz counter?

[John Mitchell]

Hi,

I would like, as part of a larger system, to implement a 32bit synchronous
binary counter. Clock frequency will exceed 100Mhz (200 would be nice)

Any hints as to which chip familly would suit??

Thanks

John

 

[Repzak]

Hi,

I would like, as part of a larger system, to implement a 32bit synchronous
binary counter. Clock frequency will exceed 100Mhz (200 would be nice)

Any hints as to which chip familly would suit??

ECL ? it is only the first couples of FF there are critical...

You could maybe think of an CPLD to do some of the work...

Kasper

 

[Rene Tschaggelar]

ECL ? it is only the first couples of FF there are critical...

nope (to the first stages) - synchroneous is the keyword.
It is the carry that makes problems. ECL definietly does
it. But there isn't much beyond an 8bit counter in a case.

You could maybe think of an CPLD to do some of the work...

While 100MHz synchroneous 32bit is not that difficult
to achieve with say an ACEX 1k , 200MHz becomes difficult.
Nowadays, I guess a cyclone will do it. A 20$ part.

Rene

 

[Joerg]

Hello John,

I would like, as part of a larger system, to implement a 32bit synchronous
binary counter. Clock frequency will exceed 100Mhz (200 would be nice)

If you don't want to use programmable logic you could employ ordinary HC
logic but make the first FF a fast one. I believe the 74LVC2G74 is
spec'd around 140MHz clock rate at 5V supply and it doesn't even cost a
quarter. You can go higher than that but then you'd either have to use
lower voltage chips or build a discrete first section. TI offers lots of
fast LV logic in case you want to go that route.

Regards, Joerg

 

[Jim Thompson]

Hello John,


If you don't want to use programmable logic you could employ ordinary HC
logic but make the first FF a fast one. I believe the 74LVC2G74 is
spec'd around 140MHz clock rate at 5V supply and it doesn't even cost a
quarter. You can go higher than that but then you'd either have to use
lower voltage chips or build a discrete first section. TI offers lots of
fast LV logic in case you want to go that route.

Regards, Joerg

I don't know quite where the frequency cross-over point is now with
"TinyLogic" parts, but CMOS may actually draw more power than (P)ECL
at high frequencies.

In my monolithic world, with no external loads, PECL beats CMOS above
about 300MHz.

...Jim Thompson

 

[Joerg]

Hello Jim,

I don't know quite where the frequency cross-over point is now with
"TinyLogic" parts, but CMOS may actually draw more power than (P)ECL
at high frequencies.

In my monolithic world, with no external loads, PECL beats CMOS above
about 300MHz.

All I could see in the LVC2G74 data sheet was the power dissipation
capacitance, 40pF at 5V. I had underestimated the chip since it can
clock a whopping 200MHz at 5V. Pretty cool for that small price.

In a counter the dissipation is often guided more by the quiescent
current. It only draws a lot while there is an input signal in the high
frequency range. Even then only the first few registers burn power while
the others stay cool.

ECL is nice but it seems that it is gradually being pushed aside by fast
LV logic.

Regards, Joerg

 

[Jim Thompson]

Hello Jim,


All I could see in the LVC2G74 data sheet was the power dissipation
capacitance, 40pF at 5V. I had underestimated the chip since it can
clock a whopping 200MHz at 5V. Pretty cool for that small price.

In a counter the dissipation is often guided more by the quiescent
current. It only draws a lot while there is an input signal in the high
frequency range. Even then only the first few registers burn power while
the others stay cool.

ECL is nice but it seems that it is gradually being pushed aside by fast
LV logic.

Regards, Joerg

Not at 2.2GHz it's not ;-)

...Jim Thompson

 

[Joerg]

Hello Jim,

Not at 2.2GHz it's not ;-)

Ok, one for you ;-)

Regards, Joerg

 

[Tam/WB2TT]

Hi,

I would like, as part of a larger system, to implement a 32bit synchronous
binary counter. Clock frequency will exceed 100Mhz (200 would be nice)

Any hints as to which chip familly would suit??

Thanks

John

You will have to come up with some scheme for fast carry generation. You
can't let it propagate through, say, 8 four bit counters. I think there are
CPLDs that will go fast enough.

Tam

 

[Rene Tschaggelar]

Hello Jim,



All I could see in the LVC2G74 data sheet was the power dissipation
capacitance, 40pF at 5V. I had underestimated the chip since it can
clock a whopping 200MHz at 5V. Pretty cool for that small price.

In a counter the dissipation is often guided more by the quiescent
current. It only draws a lot while there is an input signal in the high
frequency range. Even then only the first few registers burn power while
the others stay cool.

ECL is nice but it seems that it is gradually being pushed aside by fast
LV logic.

It advanced a bit too.
There is this 8bit synchroneous counter MC100EP016A,
doing 1400MHz, then the MC100E137, an 8 bit ripple
counter doing 2200MHz, just to name two.

Rene

 

[[email protected]]

There is a standard carry propagation scheme for fast synchronous
counters, usually shown somewhere in the data sheet, which gives the
same performance for two or more than two integrated circuits - the
chips have two count enable inputs, and one is driven by the first IC
in the stack while the other is daisy-chained.

A couple of the years ago the MC100E016 8-bit counter chip could be
guaranteed to count at 500MHz when stacked up in this way to make 16-,
24- or 32-bit counters. After that you might have to start worrying
about fan-out. More recent ECLinPS parts (referred to elsewhere in this
thread) can go faster.

 

[keith]

nope (to the first stages) - synchroneous is the keyword.
It is the carry that makes problems. ECL definietly does
it. But there isn't much beyond an 8bit counter in a case.

Gang up the 8-bit counters with look-ahead carrys. A 32 bit 100MHz
counter should be trivial these days. It would be in an FPGA,
anyway.

While 100MHz synchroneous 32bit is not that difficult
to achieve with say an ACEX 1k , 200MHz becomes difficult.
Nowadays, I guess a cyclone will do it. A 20$ part.

Even 200MHz shouldn't be a big deal in an FPGA (never used CPLDs). I
believe Xilinx' app people are over 500MHz for such things.

 

[keith]

Not at 2.2GHz it's not ;-)

Well, we're just shy of 3GHz (a few parts even above that with CMOS.
Stuff a little more complicated than counters too. The NRE is a tad on
the expensive side though. ;-)

 

[John Larkin]

Hi,

I would like, as part of a larger system, to implement a 32bit synchronous
binary counter. Clock frequency will exceed 100Mhz (200 would be nice)

Any hints as to which chip familly would suit??

Thanks

John

Spartan2E

John

 

[keith]

And the power-speed product is?

Dunno, actually. I should look it up, but I'm off until the 11th. ;-)
There's about 350M of the little buggars in there getting mighty hot and
bothered though. The real problem these days is leakage. :-(

 

[Jim Thompson]

Well, we're just shy of 3GHz (a few parts even above that with CMOS.
Stuff a little more complicated than counters too. The NRE is a tad on
the expensive side though. ;-)

And the power-speed product is?

...Jim Thompson