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What Softcore Processor Do You Use in FPGAs?

R

rickman

Jan 1, 1970
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Things got a bit busy in the other thread, so I'll start again.

I completed a routine for an interrupt handler in a hybrid
stack/register based design and it is a little smaller still than the
register based design, which also means it will run faster. Now I just
have to figure out which of these opcodes I can actually squeeze into a
9 bit instruction.

Most of the savings vs. a stack design is from being able to work
without so many stack ops, DUP, SWAP, etc, although I still need a few.
The multiply step instructions require a specific stack/register
usage, not unlike calling a Forth word where you have to put the
operands on the stack in a specific order. I could change this to make
the call easier, but I set it up to minimize the cleanup on exit. So
there are a few steps required to set that up. The register machine has
to move some data around too. Interestingly the stack machine requires
the least amount of work in this part.

Brad Eckert has been designing a stack machine or maybe it should just
be called a Forth machine since it is designed specifically to run Forth
code in addition to whatever else you want to run on it. I haven't seen
details, but it sounds similar to the MC68000 family with data size
flexibility. Not sure if it will be released for FPGA use, but once the
instruction set is out, there's nothing to stop you from rolling your
own... except patents... lol
 
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