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What is PLL "charge pump gain"?

Discussion in 'Electronic Basics' started by billcalley, Jun 23, 2007.

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  1. billcalley

    billcalley Guest

    Hi All,

    Is a PLL charge pump circuit's specification of 'charge pump gain'
    simply the maximum current that the charge pump itself can source or
    sink, or is it something else entirely? (I've looked all over for a
    clear -- and simple --explanation, but could find none!).

    Thanks,

    -Bill
     
  2. Andrew Holme

    Andrew Holme Guest

    The charge pump is a constant current source/sink controlled by the phase
    detector. The output, which is either +icp, -icp or zero, is a
    pulse-width-modulated signal, the width of which is proportional to phase
    error. Gain is normally expressed in milliamps per radian e.g. kpd =
    icp/(2*pi). So, if we had a permanent +pi phase error, the charge pump
    would output PWM with 50% duty cycle, and the average output would be icp/2.
     
  3. billcalley

    billcalley Guest


    Wow Andrew, that is the best answer I have ever gotten on any
    subject. Concise and very informative! Thank you very much!!

    Best Regards,

    -Bill
     
  4. Phil Hobbs

    Phil Hobbs Guest

    Minor point: the PD will go from 0 to +-icp in pi radians, and so the
    50% duty cycle happens at a phase error of pi/2 (one quarter cycle).

    Cheers,

    Phil Hobbs
     
  5. Andrew Holme

    Andrew Holme Guest

    It depends on the type of phase detector. For the classic PFD made from two
    D-type flip-flops and a NAND gate, gain is icp/(2*pi) as I stated in my
    previous post.
     
  6. Phil Hobbs

    Phil Hobbs Guest

    I understand that--I've used both. It's just that your post appeared to
    be contradictory. If the gain is Icp/(2*pi), then the output probably
    isn't +- Icp or 0--otherwise you could reach +- Icp at 100% duty cycle.
    No?

    Cheers,

    Phil Hobbs
     
  7. billcalley

    billcalley Guest

    While I have you two gentlemen online, another quick two
    questions, if you have a minute: 1. Is the "charge pump gain"
    specification on a PLL's data sheet the exact same thing as the
    "charge pump current" specification on other PLL data sheets?; 2.
    Does increasing the charge pump current setting on the PLL from 1mA to
    10mA decrease the lock time by 10x, or just "significantly"?

    Thanks!

    -Bill
     
  8. Andrew Holme

    Andrew Holme Guest

    Yes. Using the same symbol as in previous posts: icp is charge pump gain.
    If you increase loop gain (e.g. by increasing icp) you will increase loop
    bandwidth, and the lock time will decrease (roughly) proportionately. You
    need to make sure you don't make the loop unstable though.
     
  9. billcalley

    billcalley Guest

    Great, thanks Andrew!

    -Bill
     
  10. Jamie

    Jamie Guest

    Phase Locked Loop?
    Simply means, it compares a given variable signal with a know signal
    that can be programmed via scalars. The Variable signal normally gets
    inserted into a programmable scalar system where it then gets mixed with
    a known stable fixed signal where it can produce -/+ effects to adjust
    the variable signal oscillator to maintain it at a desired frequency..

    So, Hence the reason why they call it PLL, because, it loops around
    and gets adjusted internally to match the internal stable reference
    generator. any offset of difference produces bias voltages which can
    adjust this VCO to maintain a locked freq..
     
  11. Phil Hobbs

    Phil Hobbs Guest

    If the loop is nice and stable to begin with, the transfer function
    (gain vs frequency) crosses unity gain with a slope of pretty nearly 6
    dB per octave, i.e. near there, the loop gain is proportional to 1/f.
    (*) Small changes in gain therefore change the loop bandwidth in the
    same proportion--a 5% increase in gain will increase the bandwidth by
    pretty close to 5%. Factors of ten are another matter, though--it could
    easily become unstable, as Andrew said. It all depends on the details
    of your frequency compensation scheme.

    Most of the time, PLLs use an op amp in the loop filter, so you can get
    as much bandwidth as you can handle, irrespective of Ipd. Diode-bridge
    phase detectors have better SNR if you drive them hard, but once you put
    something as jittery as logic in there, the rest of the noise
    contributions are much less important. (Not that you can't still screw
    it up, but the PD output current isn't the important thing in general.)

    It's actually very convenient to use op amps--since we're always
    building loops that are much slower than the op amp, we can use the
    ideal op amp laws and put poles and zeros wherever we like by using
    appropriate RCs in the input and feedback elements.

    The thing that always messed me up when I started building PLLs many
    years ago was that loop gain looked like it had _units_. Kvco is in
    Hz/V, Kpd is in V/radian, and the loop amplifier's gain is
    dimensionless. Multiply them together, and you get units of Hz/radian,
    i.e. 2*pi/seconds. The thing is that the VCO is actually an ideal
    integrator--if you change its control voltage, the phase starts
    increasing by 2*pi*Kvco per second, and keeps on going. That means that
    there's a factor of 1/(2*pi*f) that you have to put in to take account
    of the frequency rolloff due to the integration. You also have to use
    the same units throughout, i.e. use volts per cycle and hertz per volt,
    or volts per radian and radians per second per volt. That way the loop
    gain comes out dimensionless, which of course it must.

    Cheers,

    Phil Hobbs

    (*) This is because if the rolloff is much faster than this, the loop
    phase shift becomes too large, and the loop stability suffers.
     
  12. billcalley

    billcalley Guest

    Thanks for the great info and tips Phil -- much appreciatted!

    Best Regards,

    -Bill
     
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