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foTONICS

Sep 30, 2011
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So I've been given an assignment to create a 4-bit parallel load, serial in/serial out shift register. Here is what I have so far:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity four_bit_par_load is
Port ( clk: in std_logic; -- clock
w_s: in std_logic:='1'; -- write/shift (writes data LOW/shifts data HIGH)
Din: in std_logic_vector(3 downto 0):="0000";--defaults to low for no undefined behaviour
Dout: out std_logic_vector(3 downto 0):="0000");--same for this one
end four_bit_par_load;

architecture Behavioral of four_bit_par_load is
signal REGI: std_logic_vector(3 downto 0);--signal used to chain together flip flops
begin

process (clk,w_s)-- I want my code to watch the clk and write/shift signals
begin
if w_s' event and w_s='0' then --if write/shift goes LOW
REGI(0) <= Din(0); --loads LSB flip flop with data
REGI(1) <= Din(1);
REGI(2) <= Din(2);
REGI(3) <= Din(3); --loads MSB flip flop with data
elsif clk' event and clk='1' then -- if clock pulse goes high then shift data right
REGI <= REGI(2 downto 0) & Din(0);
end if;
end process;
Dout(3) <= REGI(2); --this was part of the language template, not sure what it's for

end Behavioral;

So my idea was that during a HIGH "w_s" signal my data would shift right by this code:
elsif clk' event and clk='1' then -- if clock pulse goes high then shift data right
REGI <= REGI(2 downto 0) & Din(0);
end if;
and during a LOW signal it would run this code:
if w_s' event and w_s='0' then --if write/shift goes LOW
REGI(0) <= Din(0); --loads LSB flip flop with data
REGI(1) <= Din(1);
REGI(2) <= Din(2);
REGI(3) <= Din(3); --loads MSB flip flop with data

When I run the code I get the following error:
line 17: Signal REGI<0> cannot be synthesized, bad synchronous description.

Line 17 refers to the process sensitivity list, I've tried adding REGI to the list but I still get the same error. Is my problem how I'm using the signal "REGI". Am I not allowed to just give it a value like I'm doing during the if statement?
 

Harald Kapp

Moderator
Moderator
Nov 17, 2011
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Joined
Nov 17, 2011
Messages
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MY VHDL times are long ago, but let me guess anyway:
if w_s' event and w_s='0' then --if write/shift goes LOW
REGI(0) <= Din(0); --loads LSB flip flop with data
...
elsif clk' event and clk='1' then -- if clock pulse goes high then shift data right
REGI <= REGI(2 downto 0) & Din(0);
end if;
The problem here might lie in the fact that you are trying to clock the FlipFlops of the register by two different clocks.
One clock comes from
if w_s' event and w_s='0' then
essentially using the falling edge of w_S for clocking the FlipFlop.
The other clock comes from
elsif clk' event and clk='1' then
using the rising edge of clk for clocking the FlipFlops.


If you need to load the parallel data synchronously, use only one clock, namely clk. Something like this (pseudo syntax, my VHDL is very rusty. Translate to proper VHDL yourself):

Code:
if rising_edge_of_clock
   if w_s = '0'
      load_parallel_data
   else
      shift_data
endif

Or load the data asynchronously:

Code:
if w_s=´0´
   load_parallel_data
elseif rising_edge_of_clock
   shift_data
endif

I think you can omit this line
Code:
Dout(3) <= REGI(2); --this was part of the language template, not sure what it's for

And by the way: It would have been helpful to know which line line 17 actually is. You might include that information next time.
 

foTONICS

Sep 30, 2011
332
Joined
Sep 30, 2011
Messages
332
Line 17 was the process sensitivity list, namely "process(clk,w_s)"

I have made a little headway since I last posted my question, I have been able to shift the data right but haven't been able to parallel load it.

This is mainly due to me getting rid of the first part of the if statement inside the process.

I will try your suggestion of deleting that last line and not using two different clocks, will get back to you. Thanks for the help!
 
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