So I've been given an assignment to create a 4-bit parallel load, serial in/serial out shift register. Here is what I have so far:
So my idea was that during a HIGH "w_s" signal my data would shift right by this code:
When I run the code I get the following error:
Line 17 refers to the process sensitivity list, I've tried adding REGI to the list but I still get the same error. Is my problem how I'm using the signal "REGI". Am I not allowed to just give it a value like I'm doing during the if statement?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity four_bit_par_load is
Port ( clk: in std_logic; -- clock
w_s: in std_logic:='1'; -- write/shift (writes data LOW/shifts data HIGH)
Din: in std_logic_vector(3 downto 0):="0000";--defaults to low for no undefined behaviour
Dout: out std_logic_vector(3 downto 0):="0000");--same for this one
end four_bit_par_load;
architecture Behavioral of four_bit_par_load is
signal REGI: std_logic_vector(3 downto 0);--signal used to chain together flip flops
begin
process (clk,w_s)-- I want my code to watch the clk and write/shift signals
begin
if w_s' event and w_s='0' then --if write/shift goes LOW
REGI(0) <= Din(0); --loads LSB flip flop with data
REGI(1) <= Din(1);
REGI(2) <= Din(2);
REGI(3) <= Din(3); --loads MSB flip flop with data
elsif clk' event and clk='1' then -- if clock pulse goes high then shift data right
REGI <= REGI(2 downto 0) & Din(0);
end if;
end process;
Dout(3) <= REGI(2); --this was part of the language template, not sure what it's for
end Behavioral;
So my idea was that during a HIGH "w_s" signal my data would shift right by this code:
and during a LOW signal it would run this code:elsif clk' event and clk='1' then -- if clock pulse goes high then shift data right
REGI <= REGI(2 downto 0) & Din(0);
end if;
if w_s' event and w_s='0' then --if write/shift goes LOW
REGI(0) <= Din(0); --loads LSB flip flop with data
REGI(1) <= Din(1);
REGI(2) <= Din(2);
REGI(3) <= Din(3); --loads MSB flip flop with data
When I run the code I get the following error:
line 17: Signal REGI<0> cannot be synthesized, bad synchronous description.
Line 17 refers to the process sensitivity list, I've tried adding REGI to the list but I still get the same error. Is my problem how I'm using the signal "REGI". Am I not allowed to just give it a value like I'm doing during the if statement?