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Discussion in 'Electronics Homework Help' started by foTONICS, Feb 19, 2013.

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  1. foTONICS

    foTONICS

    332
    9
    Sep 30, 2011
    So I've been given an assignment to create a 4-bit parallel load, serial in/serial out shift register. Here is what I have so far:

    So my idea was that during a HIGH "w_s" signal my data would shift right by this code:
    and during a LOW signal it would run this code:
    When I run the code I get the following error:
    Line 17 refers to the process sensitivity list, I've tried adding REGI to the list but I still get the same error. Is my problem how I'm using the signal "REGI". Am I not allowed to just give it a value like I'm doing during the if statement?
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    11,533
    2,656
    Nov 17, 2011
    MY VHDL times are long ago, but let me guess anyway:
    The problem here might lie in the fact that you are trying to clock the FlipFlops of the register by two different clocks.
    One clock comes from
    essentially using the falling edge of w_S for clocking the FlipFlop.
    The other clock comes from
    using the rising edge of clk for clocking the FlipFlops.


    If you need to load the parallel data synchronously, use only one clock, namely clk. Something like this (pseudo syntax, my VHDL is very rusty. Translate to proper VHDL yourself):

    Code:
    if rising_edge_of_clock
       if w_s = '0'
          load_parallel_data
       else
          shift_data
    endif
    Or load the data asynchronously:

    Code:
    if w_s=´0´
       load_parallel_data
    elseif rising_edge_of_clock
       shift_data
    endif
    I think you can omit this line
    Code:
    Dout(3) <= REGI(2); --this was part of the language template, not sure what it's for
    And by the way: It would have been helpful to know which line line 17 actually is. You might include that information next time.
     
  3. foTONICS

    foTONICS

    332
    9
    Sep 30, 2011
    Line 17 was the process sensitivity list, namely "process(clk,w_s)"

    I have made a little headway since I last posted my question, I have been able to shift the data right but haven't been able to parallel load it.

    This is mainly due to me getting rid of the first part of the if statement inside the process.

    I will try your suggestion of deleting that last line and not using two different clocks, will get back to you. Thanks for the help!
     
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