Connect with us

VERY high speed counter???

Discussion in 'Electronic Design' started by starfire, Jul 20, 2004.

Scroll to continue with content
  1. starfire

    starfire Guest

    I need to be able to run a 32-bit counter at a 1GHz rate and periodically
    sample the count to an external circuit...

    Is there a hardware solution for this with current technology?

    Thanks.

    Dave
     
  2. Tim Wescott

    Tim Wescott Guest

    If you can stop the count to sample it you can use the MC10E137 from ON
    semiconductor -- it's a 2.2GHz clock rate /8 ripple counter. You may
    need to cascade two of them before you can get things into an FPGA...

    If you can't stop the count and you're really clever you'll figure out
    how to run two in parallel and ping-pong between them, but that's your
    problem (as is laying out the board :).

    Standard disclaimer: I've never done this, give this input as much
    value as if it came from a manager.
     
  3. Tim Wescott

    Tim Wescott Guest

    Oops -- it's an 8-stage counter; they only showed three in their diagram
    for "clarity" -- so you'll get it down to 4MHz that way, which your FPGA
    should be able to cope with. I guess this substantiates the "manager"
    crack...
     
  4. Jim Thompson

    Jim Thompson Guest

    For unusual ECL/PECL parts see...

    http://www.azmicrotek.com/

    that way you can support me also (I designed a lot of these parts ;-)

    ...Jim Thompson
     
  5. Ken Smith

    Ken Smith Guest

    The tricky bit is grabbing the count on the fly, if you have to.

    The problem is that you may get some bits just before the change and some
    just after. You can solve this by using a "switch tail" or Johnson
    counter to do the upper bits and a bit of trickery to get the lower ones.

    A Johnson counter counts 0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000
    and back to 0000. Even if you catch it updating, the error is only one
    count.
     
  6. starfire escreveu no sci.electronics.design:
    Motorola/ON Semiconductor have some ECL counters that can probably do
    this.
    I have never used any ECL, tho', just looked at them.
     
  7. There are FPGAs/CPLD going to 3.125GBit/s, AFAIK.
    The main manufacturers are Altera, Actel, Atmel Cypress, Xilinx,

    Rene
     
  8. Ian Stirling

    Ian Stirling Guest

    Random thought.
    Is there any way of interrupting commodity 1Ghz+ processors asynchronusly
    to the bus speed, so that they could do this?
     
  9. Iwo Mergler

    Iwo Mergler Guest

    Yes, but not at 1GHz.

    Modern processors take interrupts rather badly. The deep
    pipelines are a problem. There is a good chance that
    you'll be able to reach higher interrupt rates on a 40MHz i386
    than on a modern P4.

    In either case you're talking KHz, not GHz.

    Regards,

    Iwo
     
  10. Tim Wescott

    Tim Wescott Guest

    IIRC those have special hardware that can shift in a serial stream at
    that speed, but they can't do processing that fast. But if this is so
    you might be able to shift in 32 bits of samples at 3GHz and have some
    logic running at 100MHz that counts the zero crossings and adds to an
    accumulator...
     
  11. starfire

    starfire Guest

    Many thanks...

    ....and I loved the crack about managers. I'll use that one :)

    I'll check into those parts.

    Dave
     
  12. starfire

    starfire Guest

    Thanks for responding.

    I don't think I can use this counter approach, though, because I need to
    capture the actual count as an incremental number indicating a total elapsed
    time. I could probably use the counter then do a table translate in a less
    time critical section but that would be a rather large table with 32 bits...

    Thanks.

    Dave
     
  13. starfire

    starfire Guest

    I will check into this.

    If there's a part that works, I have no problem in "supporting " you... :)

    Dave
     
  14. starfire (Dave) wrote...
    Nah, the 8-stage Johnson counter is just for the high 3 bits, the rest
    you do with conventional programmable logic running at 125MHz. Some
    glue logic handles the time-delay differences between the two clocks.

    Thanks,
    - Win

    (email: use hill_at_rowland-dot-org for now)
     
  15. sycochkn

    sycochkn Guest

    could a pulse synchronizer and a parallel register be use to sample the
    output of the counter?

    Bob
     
  16. Ken Smith

    Ken Smith Guest

    I think you missed the point. You use a Johnson counter to do the upper
    bits because it can be decoded without any risk. You decode it into a the
    top few bits of the result. This allows you to grab the value on the fly
    with only a few very high speed parts in the design. If you use a power
    of 2 length, the decoding gives an even number of bits.
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-