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verilog HDL problem

Discussion in 'Electronic Design' started by babu, Jun 7, 2007.

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  1. babu

    babu Guest

    what is the error in the following code. in it the main module is
    "test". in that module's "always" block another module "counter" is
    called. but it shows error. how can i solve the problem? how can i
    call another module in always block?


    module counter(clock, reset, count);
    input clock, reset;
    output [3:0] count;

    reg [3:0] next_count,count;

    [email protected]*
    begin
    if(count<15)
    next_count=count+4'd1;
    else
    next_count=count;
    end

    [email protected](posedge clock)
    begin
    if(reset)
    count<=4'd0;
    else
    count<=next_count;
    end
    endmodule


    module test(clock,reset,count);
    input clock, reset;
    output [3:0] count;
    reg [3:0] count;
    always @(clock)
    counter(clock, reset, count);
    endmodule
     
  2. tlbs101

    tlbs101 Guest

    Hi,

    You don't need to put the counter module call in an always block, just
    instantiate it.

    module test(clock,reset,count);
    input clock, reset;
    output [3:0] count;
    reg [3:0] count;
    counter(clock, reset, count);
    endmodule
     
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