please check out this verilog code for D flip flop
when I don't use initial statement. I show error. what is use of initial statement
Code:
module d_flipflop (d,clk,q,q1);
input d;
input clk;
output q;
output q1;
reg q, q1;
always @ (posedge clk);
initial
begin
q = d ;
q1=~d;
end
endmodule
when I don't use initial statement. I show error. what is use of initial statement