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verilog code

Discussion in 'Electronics Homework Help' started by vead, Jul 25, 2014.

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  1. vead

    vead

    473
    14
    Nov 27, 2011
    please check out this verilog code for D flip flop

    Code:
    module d_flipflop (d,clk,q,q1);
    input d;
    input clk;
    output  q;
    output  q1;
    reg q, q1;
    always @ (posedge clk);
    initial
    begin
    q = d ;
    q1=~d;
    end
    endmodule 
    when I don't use initial statement. I show error. what is use of initial statement
     
  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,412
    2,780
    Jan 21, 2010
    It is used to stop you getting an error.

    Another explanation is that it is syntactically a required element.

    Another reason is that it clearly balances out the "endmodule" at the end.

    Another reason is to give the routine a name that you can refer to and to identify the interface elements.

    I think they're all pretty good reasons.
     
  3. vead

    vead

    473
    14
    Nov 27, 2011
    verilog code for half adder

    there are two type of code
    Code:
    module half_adder (a,b,sum,carry);
    input a;
    
    input b;
    
    output sum;
    
    output carry;
    
    assign carry=a&b;                        
    
    assign sum=a^b;
    
    endmodule 
    and other code
    Code:
    module halfaddert_b;
    
    reg a;
    
    reg b;
    
    wire sum;
    
    wire carry;
    
    ha uut ( .a(a),.b(b),.sum(sum), .carry(carry));
    
    initial begin
    
    #10 a=1′b0;b=1′b0;                       –This is input a=0,b=0
    
    #10 a=1′b0;b=1′b1;                        –This is input a=0,b=1
    
    #10 a=1′b1;b=1′b0;                        –This is input a=1,b=0
    
    #10 a=1′b1;b=1′b1;                         –This is input a=1,b=1
    
    #10$stop;
    
    end
    
    endmodule
    In first code we are witting only equation while second code we are putting some value

    what is difference between in this two code
     
  4. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,412
    2,780
    Jan 21, 2010
    Perhaps you should do some research on verilog syntax?

    We're not google.

    But google says this.
     
  5. vead

    vead

    473
    14
    Nov 27, 2011
    I have google .actually I have seen two type of code, one where we write only equation and other where we put some binary value. I don't understand which one code is true why we use two type of code to write verilog code
    if you can tell me the difference its good for me. I will do next step. I want to write code for encoder, decoder , multiplexer , de multiplexer please tell me which type of code I can write code 1 or code 2
     
  6. vead

    vead

    473
    14
    Nov 27, 2011
    multiplexer 2 to 1
    Code:
    s  d1  d0  q
    0  0    0    0
    0  0    1    1
    0  1    0    0
    0  1    1    1
    1  0    0     0
    1  0    1    0
    1  1    0    1
    1  1    1    1          
    Code:
    module ( s,d1, d0,q)
    input s, d1, d0;
    output q;
    reg q;
    always @( s or d0, d1);
    begin
    case (s)
    1'b0 : q= d0;
    1'b1 : q= d1
    end case
    end
    endmdule 
    
    I don't understand two statement
    1'b0 : q= d0;
    1'b1 : q= d1

    I tried in this way

    1'b0 : q= d0
    Code:
    q  d0  s
    0  0    0
    1  1    0
    0  0    0
    1  1    0
    0  0
    0  1
    1  0
    1  1
    
    Is it correct
     
    Last edited: Aug 3, 2014
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