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Verilog 2's Complement Shifter

Discussion in 'Electronic Basics' started by Davy, Feb 7, 2006.

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  1. Davy

    Davy Guest

    Hi all,

    I am new to Verilog and want to build a 2's Complement Shifter.

    I found
    %displayb(8'b0001_1000>>2); //Output 0000_0110
    %displayb(8'b1001_1000>>2); //Output 0010_0110

    So >> is unsigned shift.
    How can I build a signed (2's Complement) shift based on >>?
    i.e. I want 8'b1001_1000>>2 //Output 1110_0110

    Any suggestions will be appreciated!
    Best regards,
    Davy
     
  2. Verilog 2001 has >>> (signed shift operator)


    Best regards,
    Spehro Pefhany
     
  3. How about
    12'b1111_1001_1000>>2
    or
    { 32{b[7]}, b } >> 2
     
  4. Guest

    WHY do Verilog users post in this newsgroup ?

    Rgds
    Andrés
     
  5. Guest

    But note that the so-called "signed shift" only gives you a signed or
    arithmetic shift if it is used in a signed expression. In an unsigned
    expression, you get an unsigned or logical shift. It isn't really a
    "signed shift". It is a "shift using the signedness of the
    expression". It is what the ordinary shift operator should have been
    in the first place.
     
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