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VCC width

A

aleksa

Jan 1, 1970
0
When I started designing PCBs, I was given an advice
to route GND with 50mils and VCC with 25mils.

But now I read on the net that VCC should be wide, also.

I make two-layer digital boards only.

If I now adjust my VCC tracks to 50mils,
is there any chance of some problems?

And should I adjust? All prior boards work...

Maybe I should note that all my previous boards
were built around discreet chips, GALs, SRAM and Z80,
but am now moving towards 180 MHz ARM and FPGA.
 
A

aleksa

Jan 1, 1970
0
Problems, there always seems to be problems. Wider traces may or may
not cure your problems.

I didn't say I *have* problems, I asked
if widening a VCC *may make* problems.

The guy who suggested I should use 25mil VCC
had an old board, with DIPs, with thick GND
and thick VCC lines (some 100mils), with caps on
all chips, but the board didn't work correctly.
After he had removed the thick VCC line from
one of the chips, and soldered a thin wire,
the board worked correctly.

He also said something like "If VCC lines are
not thick, device will draw spike current from caps,
rather than the VCC line". Something like that.
I'm no expert, and I also have to translate it to English...

Anyway, I'll rephrase the question:
can widening a VCC line make problems?
 
A

aleksa

Jan 1, 1970
0
Tim Wescott said:
I need a rope to hold up a sack containing all my belongings. How thick should it be?

What? You want to know how many belongings I have, and how much they weigh, and whether any of them are alive and may make the
sack bounce and jump around? Why oh why would you want to know that, just to tell me how big a cruddy rope needs to be?

OK: I'll make a deal with you:

_You_ tell _us_ enough about what you're doing (expected current draw, more about the parts that you're going to use, whether
you're running any analog parts, etc.) Then maybe _we_ will have enough information to tell _you_ the answer that you need.

And I'll go figure out that damn rope size myself.

Perhaps you can hang yourself with it?
 
B

Bob Myers

Jan 1, 1970
0
I didn't say I *have* problems, I asked
if widening a VCC *may make* problems.

Simple answer: no, not unless there are other things wrong with
the design. Having both Vcc and ground on full planes is the norm
for 4-layer-and-up boards, you know.
The guy who suggested I should use 25mil VCC
had an old board, with DIPs, with thick GND
and thick VCC lines (some 100mils), with caps on
all chips, but the board didn't work correctly.
After he had removed the thick VCC line from
one of the chips, and soldered a thin wire,
the board worked correctly.

And at that point, SOMEONE should've thought long and
hard about just why that should be.

Bob M.
 
It's going to be interesting to try to get an ARM or an FPGA to work
on a 2-layer board. The Vcc and ground current spikes can be horrific
for a fast, many-pin chip, and a wimpy routed (non-plane) ground
structure will cause nasty ground bounce noise.

Four layers is about the minimum for decent power and signal integrity
on a high-speed board (signals, ground, power pours, signals.) 6 or 8
if you have high density or BGA parts. Most FPGAs need three power
supplies, heavily bypassed, and that will be really hard to do on a
2-layer board.

Altera's Max-2 CPLDs are available as 3.3V only, though I still wouldn't
attempt a double sided board design with them.
 
B

Bob Masta

Jan 1, 1970
0
I didn't say I *have* problems, I asked
if widening a VCC *may make* problems.

The guy who suggested I should use 25mil VCC
had an old board, with DIPs, with thick GND
and thick VCC lines (some 100mils), with caps on
all chips, but the board didn't work correctly.
After he had removed the thick VCC line from
one of the chips, and soldered a thin wire,
the board worked correctly.

He also said something like "If VCC lines are
not thick, device will draw spike current from caps,
rather than the VCC line". Something like that.
I'm no expert, and I also have to translate it to English...

Your translation is just fine, and what he said
makes a certain amount of sense. He's saying that
the resistance of the Vcc lines plus the bypass
capacitors act as RC filters on each chip, so if
one chip draws a current spike it is "handled"
from its own local C with less disturbance of the
Vcc for other chips.

The question is whether this approach is better
than using a fat Vcc trace (low R) whose voltage
doesn't move around as much in response to spikes
in the first place. My guess is that his approach
may have made a difference on a marginal design,
but the next design might have a completely
different behavior.
Anyway, I'll rephrase the question:
can widening a VCC line make problems?

Maybe, if you have a marginal design or layout.
But if you are looking for a general design rule,
I'd go with fat ground and Vcc as the best bet to
avoid the most problems.

Best regards,


Bob Masta

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A

aleksa

Jan 1, 1970
0
John Larkin said:
It's going to be interesting to try to get an ARM or an FPGA to work
on a 2-layer board. The Vcc and ground current spikes can be horrific
for a fast, many-pin chip, and a wimpy routed (non-plane) ground
structure will cause nasty ground bounce noise.
Make the ground and Vcc as wide as you can, and stitch them with lots
of bypass caps. Lots of luck.

I have a working FPGA board, Spartan II XC2S50 TQFP144.
If I replace the PC with ARM, I could even use VQFP100.
The freq is not much, 40 MHz, and I doubt I'll go higher than that.

I've placed vias on every VCC/GND pair and placed caps on the bottom
side. The bottom side is almost free of signals, so there's no problem
connecting the power.

As for the ARM @ 180 MHz... well let's wait and see.
I hear other people made it.
 
A

aleksa

Jan 1, 1970
0
George Herold said:
Tim Wescott probably knows a lot more about electronics than I do....
If you're nice he might help you.

I can't be nice to someone who isn't nice to me.

I asked "can widening a VCC cause problems" and not
"how to calculate needed trace thickness".
 
A

aleksa

Jan 1, 1970
0
Bob Masta said:
The question is whether this approach is better
than using a fat Vcc trace (low R) whose voltage
doesn't move around as much in response to spikes
in the first place. My guess is that his approach
may have made a difference on a marginal design,
but the next design might have a completely
different behavior.

Its easy when you have a 4-layer board, but
when you have a 2-layer board you can't
always use thick GND *and* thick VCC.
That was another reason to use thiner lines.

Since I now use smd parts only, all signals are on
top layer so there's plenty of space on the bottom.

Thats why I asked if I should widen my
VCC lines from now on.
 
L is usually more important than R.
Its easy when you have a 4-layer board, but
when you have a 2-layer board you can't
always use thick GND *and* thick VCC.
That was another reason to use thiner lines.

You can't always use a 2-layer board. I wouldn't *think* of it for any
high-speed digital devices, like FPGAs (though the I/Os can often be tuned
down). Even four layers is cutting it close.
Since I now use smd parts only, all signals are on
top layer so there's plenty of space on the bottom.

Thats why I asked if I should widen my
VCC lines from now on.

As wide as possible, absolutely. Cuts down on the L.
 
I have a working FPGA board, Spartan II XC2S50 TQFP144.
If I replace the PC with ARM, I could even use VQFP100.
The freq is not much, 40 MHz, and I doubt I'll go higher than that.

The clock frequency isn't (usually) the issue; how fast are your edges?
I've placed vias on every VCC/GND pair and placed caps on the bottom
side. The bottom side is almost free of signals, so there's no problem
connecting the power.

The total distance from the pin to the cap and cap to ground is what matters.
As for the ARM @ 180 MHz... well let's wait and see.
I hear other people made it.

Again, the core frequency doesn't matter, much. The package should be
designed well enough to handle that part. Your problem is managing the
delta-I on the power, ground, and signals.
 
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