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Variable phase shifter?

Discussion in 'Electronic Design' started by Tom Bruhns, Aug 15, 2008.

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  1. Tom Bruhns

    Tom Bruhns Guest

    (Need a register between the counter and the DAC...)

    Let's see--instead of a counter to get the period and a DAC to turn
    that into an analog voltage--why not just a ramp that's reset by the
    square wave, and a peak detector to monitor how big the ramp gets?
    The peak detector output is proportional to the waveform's period.
    It's kind of the analog of a frequency-to-voltage converter, but it's
    a period-to-voltage converter. You don't really even need a peak
    detector; a simple average (e.g., long time constant RC filter) will
    do fine, since the frequency doesn't change in use and I can in this
    case depend on the stability of the duty cycle of the input.

    But how I turn the 555's output to a delay (on a 120MHz square
    wave...), I'm a bit foggy on...

    On the other hand, I know how to use a voltage to control a wideband
    delay pretty this has some possibilities. Thanks for the

  2. You were saying you're more interested in the timing than the waveform. If
    the 1.2 MHz had, say, a 60% duty cycle, you could just use the 555 to
    generate the delay pulse, and a simple NAND with the original waveform
    would give you a delayed square wave, but the duty cycle of the second wave
    would be variable.
  3. Tom Bruhns

    Tom Bruhns Guest

    That's OK at 1.2MHz, but what about at 120MHz, 8 nanosecond period??
    Then we're back to about the same method I was suggesting earlier,
    using fast comparators on a fast ramp; I think it's about the same as
    your 555 idea, but with the comparator as a stand-alone part. Does
    anyone make an "ECL 555"?? ;-) I do appreciate all the inputs--I'm
    coming up with something simpler than I originally would have because
    of them.

  4. JosephKK

    JosephKK Guest

    The more i read about this the more i think that a useful approach is
    an FPGA implementing a hybrid delay locked loop and PLL for that
    frequency range and that phase range. For the 120 MHz end you would
    need really fast IO, but not so many pins.
  5. Tom Bruhns

    Tom Bruhns Guest

    Yes, that's certainly one reasonable way to go. I don't think any
    modern FPGA would have a problem with the speed, though--certainly not
    the ones we've been using around here. Actually, once you've invoked
    an FPGA, you also have opened the door to running an NCO with fine
    phase adjustment inside it...

    My thanks to all who have provided inputs.

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