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Using CMOS logic devices w/ parallel port

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Bart T.

Jan 1, 1970
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Hello,

I'd like to build some circuits and interface them to my PC's parallel
port but I'm still very much a beginner and have some questions.
Before I build anything complicated that'll be difficult to debug, I
wanted to start with something simple: A serial -> parallel -> serial
circuit consisting of a 74HC165, 74HC164, and an HC octal D-tyle flip
flop. Data will be input serially via the parallel port, then, the
clock on the flip flop will be triggered to latch the data, and
finally, the second shift register will be used to grab the 8 bits and
shift them back to the parallel port serially. Hopefully, the data
that comes back is the same as what was sent :)

I'm doing this to familiarize myself with HC devices. Here is where
I'm confused:

1. The parallel port lines are TTL but the HC ICs are CMOS. I've read
that using a pull up between the signal line and Vcc will pull the
voltage up to Vcc levels. I understand why pull ups work in many
situations, but I don't understand how it's possible for this to work
if the TTL output is, say, 2V and the Vcc is 5 -- won't current flow
across the resistor dropping the voltage down back to 2?

How should the resistance be calculated? I've seen a lot of designs
that use 2.2k-ohms. Is this to limit the current to around 2.4mA? I
can't remember if that's the max that a parallel port line can safely
be assumed to sink (that's what the resistor is for after all, right?
The CMOS inputs don't sink any current if I understand correctly.)

2. If I need to tie an input high, can I connect it directly to Vcc? I
have a text book which says that for TTL logic, a resistor should be
used to limit the voltage to the minimum input high voltage (in order
to limit current into the TTL input.) Does this apply for CMOS? I've
been assuming that CMOS inputs don't actually draw any current and
thus the resistor would be useless.

3. I'm aware that capacitors are needed between each chip's Vcc and
Gnd connections, but I don't understand the details and therefore
don't know how to calculate the capacitance. I also read that
capacitors should be used to prevent interference on clock and reset
lines of HC devices:
http://www.smspower.org/smsreader/troubleshooting.html (see the first
problem.)

For reset and clock lines, I imagine the capacitor would be connected
between the signal line and ground as close to the IC as possible. The
site I linked to does not actually show where to connect them on any
schematic, just on the physical board itself, and I haven't converted
the author's coordinates to determine which lines are being affected.

I'm not sure what interference looks like so I'm not entirely certain
how the capacitor serves to minimize its effects. I've only dealt with
capacitors in very simple RC and RLC circuits.

4. CMOS outputs can safely go to CMOS inputs -- right? I don't think
any of the devices I'm going to be using have open collector outputs
or anything like that.

5. Finally, I'll actually be using a 6V Vcc (4 AAA batteries -- easier
for me to build it this way.) I could use a voltage divider if really
necessary but I think I should be safe for this project if I assume a
5V Vcc and connect to 6V anyway, right?

Thanks in advance. I hope someone can help me out and give me some
pointers here :)
 
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