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Tri State Devices

Discussion in 'Electronic Basics' started by Abstract Dissonance, Feb 27, 2006.

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  1. Is a Tri State "driver"(I think thats what its called) basicaly a device
    which lets you set either Low Z or High Z?

    something like

    C
    |
    |------|
    A ---| |--- B
    |------|


    Where, say, if C is high then A and B see a high Z(open circuit) and if C is
    low then it acts like a low Z? (a short)


    or maybe they are only unidirectional?

    But basicaly it is like a controled switch?


    The reason I ask cause in a circuit they have something like



    D2 >------------+
    |
    |
    |------|
    D0 >---------| |---+----- Data
    |------| |
    |
    ACK >-------------------+

    Where the device is 74LS244.


    Only thing I can figure out is that D2 acts like a control that lets D0 pass
    through or not. If its off then ACK "senses" the Data...

    i.e.,

    So D2 off(or on if inverted) would allow D0 to send data through to Data...
    and ACK could "sense" this if it wanted... if D2 was on then D0 couldn't
    send anything and ACK could then be used "sense" output comming from Data.

    So, in a sense it lets Data be used as an input and output port... but
    without the device then data could go to D0 and if D0 is only an output it
    will be recieving input which might screw it up?


    Is that the basic idea?

    Thanks,
    Jon
     
  2. PeteS

    PeteS Guest

    A tristate driver ( a registered trademark of National Semiconductor,
    incidentally) has three possible states (giving it the name).

    High.
    Low
    These are the output states of normal logic

    High-z. This means the output buffer is 'disconnected' from the output
    pin (and therefore any circuitry hanging off it).

    In all cases, it may be looked at as a controlled switch, where the
    output may be disconnected.

    Found in many an application (most commonly in bussed applications, but
    often elselwhere).

    This permits mutiple *outputs* to be connected together, with the
    designer setting it up so only one can be active at any time. For lower
    speed to do the same thing, we used to use open collector / open drain
    (and for ECL open emitter) techniques.

    Most memory devices (even those that are read only) have tristate
    outputs, which become active on some mixture of control signals
    (usually output enable + chip select). Buffers and transceivers also
    have this when designed for use in such a system.

    Another very popular use is to buffer signals across power domains,
    such that if a particular domain is unpowered, the signals are buffered
    through a tristate device that is held in tristate, preventing power
    bleed across domains.

    Without seeing the entire schematic you are referring to, it's hard to
    know just what the designer was trying to achieve.

    Cheers

    PeteS
     
  3. blah

    blah Guest

    They are unidirectional (A->B) in your case, and digital only. They
    shouldn't be thought of as a switch as they aren't. It's a digital buffer
    whose output drive can be shut off.
    I think thats a bad description, since a pass-gate is much more similar to
    a "controlled switch".
    The schematic you drew is essentiall a bidirectional I/O. "ACK" sees
    whatever is on the Data line. If D2 is asserted the tristatable buffer
    asserts D0 onto Data. The theory here being that if you want to read, you
    shut off D2, and Ack will have valid data being asserted from off the
    schematic. If you want to write a value, D2 is asserted and D0 is
    buffered through to Data. Ack will still be a valid read, but it will
    simply read back D0.

    One of the more common applications for this is on bidirectional busses.
    For instance on the ISA bus, the CPU may want to pass data to the
    peripheral boards by asserting D2, and then it may want to allow the
    peripheral boards to pass data back to it over the same lines by
    de-asserting.
     
  4. John Fields

    John Fields Guest


    ---
    If it were to be done with relays, here's how it would work:


    +V GND
    DATA>------+ | |
    | O--> |<--O
    [COIL]- - -|
    | O
    GND |
    |
    OE>--------+ |
    | O
    [COIL]- - -|
    | O--> |
    GND |
    +------->OUT



    DATA | OE | OUT
    -------+----+-----
    GND GND HI-Z

    +V GND HI-Z

    GND +V GND

    +V +V +V

    HI-Z meaning that OUT is floating.
     
  5. Ok, Makes sense. Basicaly thats what I was thinking but I couldn't say it
    properly.

    Thanks,
    Jon
     
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