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Transmission Gate question

Discussion in 'Electronic Basics' started by Angmor, Jan 31, 2006.

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  1. Angmor

    Angmor Guest

    I've been staring at a transmission gate circuit for a while trying to
    figure out how it works and I'm not making any progress. The problem
    we have (yes, it's a homework problem) is to determine the on
    resistance for the specific gate we've been given. The circuit diagram
    is basically just an nmos and a pmos connected in parallel. The input
    side (I know they're interchangable) is set to 5V and both of the fets
    are on (5v & 0v gate for n/p, respectively). No output voltage is
    given. I've searched for a while on google trying to find helpful
    information, but all I can find is that the input signal is supposed to
    pass through to Vout so that Vout is almost equal to Vin.

    My question is... How can I determine the output voltage? I can't
    determine the transistor mode or currents without the output voltage,
    and if I can't do that I cannot determine the on resistance. I am not
    asking for an answer to my problem, I would just like a nudge in the
    right direction if possible. This problem is driving me crazy.
     
  2. Angmor

    Angmor Guest

    Something I didn't make entirely clear.... I don't understand how they
    can just state that the output voltage follows the input voltage
    closely. Where is the justification? This is the real problem I'm
    having.
     
  3. Pooh Bear

    Pooh Bear Guest

    When the fets are on clearly this must be the case ( assuming the load is
    much greater than the fets' on resistance of course - which is how you use
    these things ).

    Graham
     
  4. Noway2

    Noway2 Guest

    Fets are controlled by the gate source voltage Vgs and its relationship
    to the threshold voltage. When the fets are fully turned on, they act
    as a resistance equivalent to the Rds-on parameter. Think of the
    devices as being switches, either on or off and then modeling them as a
    small or large resistance.

    Be aware, the input - output side of the fets (drain and source) are
    not really interchangable. I was taught that they were in school and
    got bit by this on a circuit board design. The result was $500 and two
    weeks down the toilet. I didn't understand it at first, until I
    realized I was trying to turn the device on by controlling Vds not Vgs.

    Most text books focus too much on the Id = k(Vgs - vt)^2 equation.
    Unless you are getting into semiconductor physics, this equation is
    probably about worthless. It may help for you to look at some product
    data sheets for fets and look at the curves relating on resistance
    versus the Vds and Vgs.
     
  5. What happens to the bulk when you "turn the transistor on"?

    What circuit node is the output terminated to, and through what (load)?

    IOW first find what limits the output voltage can be within and go
    from there.


    Mark L. Fergerson
     
  6. Pooh Bear

    Pooh Bear Guest

    Noway2 wrote:

    Some JFET types are so interchangeable though. e.g Siliconix J111, J174
    familes

    Graham
     
  7. Guest

    Guest Guest

    : My question is... How can I determine the output voltage? I can't
    : determine the transistor mode or currents without the output voltage,
    : and if I can't do that I cannot determine the on resistance. I am not
    : asking for an answer to my problem, I would just like a nudge in the
    : right direction if possible. This problem is driving me crazy.

    Not true. You only need the gate voltage and the source voltage
    to determine the current. You can "guess" at the drain voltage and see
    what happens. What you will find is that the drain voltage doesn't matter
    (in this case.)

    Let's look at the NMOS first. NMOS vg = Vdd. Suppose NMOS Vs
    (input signal) = 0V. NMOS Vgs = Vdd. Let's consider 3 possibilities for
    NMOS Vd (output signal): Vd = Vs = 0V, Vd = Vdd, and Vd is somewhere
    between Vdd and 0. If Vd = 0V, Vds = 0V. With Vgs = Vdd, and Vds = 0V,
    the NMOS device is in the linear region with a Vds of 0V, which implies
    that Id = 0 (something that you would expect of a floating transmission
    gate, right?.) Now suppose that Vd = Vdd. Now Vds = Vdd. With Vgs =
    Vdd, and Vds = Vdd, the NMOS must be in saturation, because Vds > Vgs -
    Vt. In saturation, Id = beta/2 * (Vgs - Vt)^2. This means that a current
    would be flowing from drain to source, which is not something that you
    would expect (in the steady state) of a floating transmission gate. Now,
    suppose that Vd = Vdd - Vt - delta (where delta is some very small
    number.) With Vgs = Vdd, and Vds = Vdd - Vt - delta, the NMOS is in the
    linear region, and has Id = beta * (Vgs - Vt)*Vds - Vds^2/2. There will
    be a non-zero current flowing from drain to source, which, again, is not
    something you would expect from a floating transmission gate.

    I'll leave the analysis of the PMOS to the reader, but it is
    nearly identical. In my reasoning, I assumed that the "output" (i.e. one
    side) of the transmission gate was floating. I forget if this was the
    case in your original problem. What I mean by floating is that it is
    connected to a load that is high impedance at DC. THis could be an actual
    open circuit, or something that looks like one at DC (like a capacitor
    connected between the output and ground, which is the case if it is
    driving the input of a CMOS gate.) If this is not the case, the analysis
    is a little diffrerent, but you can use the same techniques to prove this
    to yourself.

    Hope that helps,

    Joe
     
  8. Guest

    Guest Guest

    : Most text books focus too much on the Id = k(Vgs - vt)^2 equation.
    : Unless you are getting into semiconductor physics, this equation is
    : probably about worthless. It may help for you to look at some product
    : data sheets for fets and look at the curves relating on resistance
    : versus the Vds and Vgs.

    It's more a distinction between analog and digital circuits,
    rather than semiconductor vs (? -- MOSFETs are semiconductors.) Devices
    in CMOS digital circuits spend most of their time in either the cutoff or
    the linear region, only passing through the saturation region (whose drain
    current is roughly given by the equation you presented above) when they
    are switching. On the other hand, most useful analog circuits involve
    amplifiers, which rely on devices that exhibit the controlled
    current-source behavior characteristic of the saturation region of
    operation.

    Joe
     
  9. I think you mean "linear" where you say "saturation" and vice versa.
     
  10. notme

    notme Guest

    As with most non-linear, it requires somewhat of a leap of faith. We have
    to make an assumption about the behavior of the circuit, so lets assume
    the book is right. If the output follows the input, then essentially by
    definition Vds is going to be very small. The point of putting 5V and 0V
    on the gate is to maximize Vgs, therefore its likely that (Vgs-Vth)>Vds.

    Bear in mind that you have a complimentary setup here. If the input
    voltage were very high (say 4.8V), then Vgs-Vth on the NMOS may actually
    be negative, but in the same instance for the PMOS it will be very large.
    So using complimentary transistors should keep one of the transistors
    in the linear region at all times.

    for linear region: Ids=Beta((Vgs-Vth)*Vds-Vds^2/2)

    Now, consider on resistance is Rds. R=dV/dI.

    it is probably easier to take dI/dV and invert. We get 1/(Beta*((Vgs-Vth)
    - Vds)) If we assume Vds is small, then that term drops out and we see
    that the resistance is almost completely dependent on Beta*(Vgs-Vth).
    Now, what happens if your input voltage gets very high or low... Well,
    you first go into saturation, and then cutoff. The standard simple models
    don't work well in cutoff, so we'll just say the resistance is infinite
    there. In the case of saturation Ids=Beta/2*(Vgs-Vth)^2*(1+Lambda*Vds)
    So now we have 1/(Beta/2*(Vgs-Vth^2)*Lambda). While, t-gate transistors
    are typically quite small to minimize capacitance, the lambda is still
    likely pretty small compared to unity, so the resistance of that
    transistor goes way up. At the same time, the complimentary transistor is
    likely to be on pretty hard, so when you put them in parallel the
    saturated transistor's contribution to overall resistance is fairly small.

    Now, what if the books statement was wrong. Well, in order to have a
    substantial Vds you'd have to be loading the t-gate quite heavily compared
    the Rds you calculated above. At some point as you increase the load
    (decrease the load's resistance to ground), the Vds will keep growing and
    they will become saturated. At that point, the circuit starts working
    poorly. But now that you know how T-gates work, you should be able to
    design them such that you don't allow Vds to get large, hence making them
    work much less effectively.

    As for the other people who made some claims such as:

    1) Drain and Souce aren't interchangable.... Thats absurd, of course they
    are. Transistors are four terminal devices, and the source and drain are
    completely interchangable. In the case of an N-MOS transistor the source
    is whichever terminal is at a lower voltage, and in the case of a P-MOS
    its whichever terminal is at a higher voltage. In the case of some
    discrete transistors, in order to minimize pin count, they tie the bulk to
    the source internally, thereby making it a 3 terminal device and making it
    non-symmetric. However, that doesn't mean that the transistor terminals
    aren't interchangable, just some packages aren't.

    2) Saturation is only useful for semiconductor physics?! How the heck do
    you think people make current mirrors? With MOSFETS in triode? Get real,
    a transistor is a transistor, its not a switch, or a resistor, or anything
    else. They are wonderful devices which can be operated in a number of
    different regions and be used for many different things.

    3) Joe's claims that digital circuits spend most of there time in linear
    or cut-off region and only transition through saturation is completely
    correct. He didn't mix up saturation and linear. The problem arises
    because most people don't understand what saturation and linear region of
    a MOSFET really mean. They describe e-field configurations on a MOSFET,
    not how "on" a device is or such.
     
  11. John Larkin

    John Larkin Guest

    What do you mean by "we've been given"? Were you given a physical
    part, or a chip layout, or something else?

    If it's a physical part, use an ohmmeter!

    John
     
  12. Angmor

    Angmor Guest

    We were given a circuit diagram with a floating input and a floating
    output, so an ohmmeter isn't an option. Thank you everyone for the
    replies, they've been helpful.
     
  13. Angmor

    Angmor Guest

    We were never actually told that the circuit was a transmission gate.
    I only found that out by browsing through the book. For the homework
    we're supposed to analyze it assuming no prior knowledge of
    transmission gates. Therefore for all we know the resistance could be
    1 MOhm, so it doesn't seem possible to make any reasonable assumptions
    about the source voltage in this case. Am I wrong? I've read over
    these posts multiple times, and it always seems to come down to
    assuming the truth of what the book states. Unfortunately we were not
    told that the voltage passes through, that was just something I read
    online. Am I missing information in this problem? Without know the
    resistance of the circuit I can't justify my output voltage
    assumptions, and without knowing the output (Source) voltage I can't
    determine the resistance. My apologies if I'm missing something that
    was posted, I'm just trying to get this through my head.
     
  14. Angmor

    Angmor Guest

    On other thing.. we were however told to find the "on-resistance," is
    that enough to assume Vds is small?
     
  15. Jasen Betts

    Jasen Betts Guest

    attach a reasonable load to the output.

    the on-resistance may somewhat load-dependant.

    Bye.
    Jasen
     
  16. Guest

    Guest Guest

    : I think you mean "linear" where you say "saturation" and vice versa.

    Nope. In a MOSFET, the linear (also called triode or
    non-saturation) region occurs when Vds < Vgs - Vt. The drain current is
    given by Id = beta * [(Vgs - Vt)*Vds - Vds^2/2]. If you assume that Vds
    is small, you can neglect the Vds^2 term, and the drain current is linear
    with respect to Vds, hence the name linear region. If you don't neglect
    the Vds^2 term, the drain current is obviously not linear, but that's
    where the name comes from.

    In the saturation region, (when Vds > Vgs - Vt) the drain current
    does not vary with respect to Vds (at least to first order,) so it is
    saturated at its maximum magnitude.

    This is reversed from BJT nomenclature, where the forward active
    region of a BJT is somewhat analogous to the saturation region of a
    MOSFET, and the linear region of a MOSFET is somewhat analogous to the
    saturation region of a BJT.

    Joe
     
  17. Rich Grise

    Rich Grise Guest

    The on resistance is listed on the data sheet for the part. In a data
    sheet for a single MOSFET, it's listed as "Rdson", for "resistance,
    drain-to-source, while conducting as hard as it can".

    According to what we've been able to extract from you, that's the only
    answer that makes sense.

    What is the actual text, word-for-word, of the test question?

    Good Luck!
    Rich
     
  18. nothanks

    nothanks Guest

    Unfortunately, in engineering you have to make assumptions about all sorts
    of things because problems aren't completely specified. I was just
    reading a book in which they were talking about how a spring is only
    mostly linear. At some point if you exert a "large" amount of force on
    it the spring breaks and ceases to be even remotely linear, permanently.
    Unfortunately, its very difficult to analyze non-linear or multi-modal
    things (whether they be circuits, control systems, what have you), so as
    engineers you often have to make the problem more managable and reasonable.
    Make assumptions and approximations. Linearize things about an operating
    point, etc. The small angle approximation, sin theta = theta and cos
    theta = 1 for smallangles is an excellent example. Is it completely right?
    No... Is it close enough? For a lot of things, yes. There is going to be
    plenty of uncertainty in the answer anyway, since your value of K and Vt
    are never going to be fully known.

    However there are things to bear in mind regarding assumptions and
    approximations.

    1) It often takes experience and education to learn whats reasonable and
    whats not.

    2) You should always state what assumptions and approximations you made
    while solving a problem, and you should be able to justify them.

    3) You should *ALWAYS* verify your answer and make sure that the
    assumptions you made are reasonable given the answer you came up with. If
    you are using the small angle approximation and realize that at some
    point, theta is 1, then the small angle approximation is probably not
    justifiable.

    You do have the question of what is Vds... Its a lot easier to solve this
    problem if you assume Vds is small than its large. So assume its small,
    solve the problem and then go back and see if its a justifiable
    assumption. If you find that Rds is about 100 ohms. Then you can say
    that the solution you have is probably a reasonable as long as the load
    resistance is > 1000 ohms. So thats your answer, the Rds is about 100
    ohms so long as the load is > 1000. Thats a reasonable answer. It's not
    a perfect answer, but its unlikely you'll be driving a load much heavier
    than that, so its good enough. On the other hand you may find that Rds is
    1 MOhm, and decide that its not a reasonable assumption and then you have
    to go back and come up with a more complicated solution.

    Now, you are right that they don't specify Vs and it will impact the Rds,
    but my guess is because of the complimentary nature of the architecture.
    It won't make that much difference. Its reasonable to assume Vs is
    somewhere between 0 and 5V because the gate voltage is probably coming
    from digital logic which is going to drive the gate to the rails of the
    circuit. So pick some values of Vs and see if it makes a difference. Go
    with 0V, 2.5V and 5V, that probably gives you a pretty complete range of
    answers (all P-fet, all N-fet, and half each).
     
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