Connect with us

Transistor Veb rating... plus Patent Update

Discussion in 'Electronic Design' started by Genome, Feb 15, 2007.

  1. Genome

    Genome Guest

    This could almost be a first in that I don't often ask questions. Some of
    you might remember my mention of a Patent what I have applied for. If you
    don't then an explanation about it is here.

    http://www.genomerics.org/patent/patent.html

    I'm going to be putting up another page with a refined PFC circuit using a
    modified method to achieve the same result later on.... soon. This one will
    show a full model of a 2kW PFC circuit operating off a 90V line at 100KHz
    with an IGBT with main power semiconductor losses in the order of 60W.

    That's 97% efficiency..... It might get better than that if I used an SiC
    diode but, at the moment, I'm implementing resonant turn off of the diode
    and that's costing me 20W...... I wouldn't go so far as to say I'll get the
    losses down to 40W as a result because I'll suffer switching losses
    elsewhere.... and, of course this is just modelling.

    Anyway, as I mention on the first page, I'm bothered about the Veb rating of
    the transistor in the IGBT. I've had a 'touch' from a semiconductor
    manufacturer and this problem has been mentioned. The concern is the figure
    itself and possible reliability issues when driving the device as I have
    suggested, they have no long term figures for this kind of operation.......

    There are other 'issues' but for the moment this is the one I am looking
    into. I suppose I should just accept that that is the problem. These people
    have more experience than I do and therefore it is a non-starter......
    However I do know that power switching transistors are operated in this way,
    although there was some mention of differences in manufacturing in
    particular passivation, with Veb being applied to achieve fast turn off.

    Anyway, I'm off for a trog about the web to see if I can find any
    information relating to reverse bias operation of IGBTs giving limits and
    reliability information. I'm afraid my natural assumption is this is either
    a wool pulling excercise or the person I am dealing with might be mumbling
    because they are not absolutely certain themselves.

    Specifically I'm looking for ratings and limits for transient rather than DC
    operation. If anyone has thoughts on this or can point me in the direction
    of something to read then I'd appreciate it.

    Obviously, for those who care or Don Lancaster, I'm not losing sleep or
    money over this. Just time and my time is free.

    Thanks

    DNA
     
  2. Gibbo

    Gibbo Guest

    [snip]

    A couple of points I noticed.

    Just 1% leakage in the mutual coupling removes all the "suckage".

    Assuming you can solve that then adding D1 and R7 as below will lose you
    a touch in efficiency but allow you to limit the "suckage" current to a
    safe level (if you manage to find out what that "safe" level is).

    Version 4
    SHEET 1 2568 1700
    WIRE 720 240 368 240
    WIRE -208 304 -272 304
    WIRE 112 304 -128 304
    WIRE 160 304 112 304
    WIRE 368 304 368 240
    WIRE 368 304 240 304
    WIRE 416 304 368 304
    WIRE 592 304 480 304
    WIRE 368 336 368 304
    WIRE 720 336 720 240
    WIRE 32 432 -48 432
    WIRE 288 432 240 432
    WIRE 368 432 368 400
    WIRE 400 432 368 432
    WIRE 32 464 32 432
    WIRE 288 464 288 432
    WIRE 368 464 368 432
    WIRE 720 464 720 416
    WIRE 720 464 368 464
    WIRE 112 480 112 304
    WIRE 368 480 368 464
    WIRE -272 496 -272 304
    WIRE 592 496 592 304
    WIRE 32 560 32 544
    WIRE 32 560 -48 560
    WIRE 64 560 32 560
    WIRE 288 560 288 544
    WIRE 288 560 208 560
    WIRE 320 560 288 560
    WIRE -272 608 -272 576
    WIRE 112 608 112 576
    WIRE 112 608 -272 608
    WIRE 368 608 368 576
    WIRE 368 608 112 608
    WIRE 592 608 592 576
    WIRE 592 608 368 608
    WIRE 592 640 592 608
    WIRE -240 688 -272 688
    WIRE -128 688 -160 688
    WIRE -96 688 -128 688
    WIRE 0 688 -16 688
    WIRE 80 688 64 688
    WIRE 112 688 80 688
    WIRE 320 688 176 688
    WIRE 352 688 320 688
    WIRE -272 720 -272 688
    WIRE 176 720 176 688
    WIRE 512 736 480 736
    WIRE 640 736 512 736
    WIRE 896 736 800 736
    WIRE 896 752 848 752
    WIRE 976 752 960 752
    WIRE 512 768 512 736
    WIRE 544 768 512 768
    WIRE 848 768 848 752
    WIRE 896 768 848 768
    WIRE -128 784 -128 688
    WIRE -48 784 -128 784
    WIRE 80 784 80 688
    WIRE 80 784 16 784
    WIRE 544 784 512 784
    WIRE 640 784 608 784
    WIRE 848 784 848 768
    WIRE 896 784 848 784
    WIRE 976 784 960 784
    WIRE 512 800 512 784
    WIRE 544 800 512 800
    WIRE 848 800 848 784
    WIRE 896 800 848 800
    WIRE 512 816 512 800
    WIRE 544 816 512 816
    WIRE -272 832 -272 800
    WIRE 512 832 512 816
    WIRE 512 832 480 832
    WIRE 544 832 512 832
    WIRE 720 896 720 832
    WIRE 720 896 496 896
    WIRE -240 944 -272 944
    WIRE -128 944 -128 784
    WIRE -128 944 -160 944
    WIRE -96 944 -128 944
    WIRE 80 960 80 784
    WIRE 80 960 -32 960
    WIRE 176 960 176 800
    WIRE 208 960 176 960
    WIRE -96 976 -128 976
    WIRE 176 1008 176 960
    WIRE 976 1008 672 1008
    WIRE 112 1024 112 688
    WIRE 112 1024 64 1024
    WIRE 128 1024 112 1024
    WIRE 672 1040 672 1008
    WIRE 752 1040 672 1040
    WIRE 848 1040 848 800
    WIRE 848 1040 816 1040
    WIRE 976 1040 848 1040
    WIRE 112 1072 64 1072
    WIRE 128 1072 112 1072
    WIRE -272 1088 -272 944
    WIRE 112 1088 112 1072
    WIRE 320 1088 320 688
    WIRE 672 1088 672 1040
    WIRE -272 1200 -272 1168
    WIRE -128 1200 -128 976
    WIRE -128 1200 -272 1200
    WIRE 112 1200 112 1168
    WIRE 112 1200 -128 1200
    WIRE 176 1200 176 1088
    WIRE 176 1200 112 1200
    WIRE 320 1200 320 1168
    WIRE 320 1200 176 1200
    WIRE 672 1200 672 1168
    WIRE 672 1200 320 1200
    WIRE 752 1200 752 1056
    WIRE 752 1200 672 1200
    WIRE 752 1232 752 1200
    FLAG 240 432 ADRV
    IOPIN 240 432 In
    FLAG 64 1072 VTRI
    IOPIN 64 1072 Out
    FLAG 480 736 PWM
    IOPIN 480 736 In
    FLAG 976 752 ADRV
    IOPIN 976 752 Out
    FLAG 64 1024 VCEA
    IOPIN 64 1024 Out
    FLAG 208 960 PWM
    IOPIN 208 960 Out
    FLAG 912 800 0
    FLAG -272 832 0
    FLAG 976 784 NDRV
    IOPIN 976 784 Out
    FLAG 720 688 0
    FLAG 496 896 BDRV
    IOPIN 496 896 In
    FLAG 560 832 0
    FLAG 976 1040 CLB
    IOPIN 976 1040 Out
    FLAG 976 1008 BDRV
    IOPIN 976 1008 Out
    FLAG 480 832 CLB
    IOPIN 480 832 In
    FLAG 208 560 GT1
    IOPIN 208 560 Out
    FLAG -48 432 BDRV
    IOPIN -48 432 In
    FLAG -48 560 GT2
    IOPIN -48 560 Out
    FLAG 592 640 0
    FLAG 640 832 0
    FLAG 752 1232 0
    FLAG 400 432 VCE
    IOPIN 400 432 Out
    FLAG 352 688 15V
    IOPIN 352 688 Out
    SYMBOL Opamps\\opamp -64 896 R0
    SYMATTR InstName CEA
    SYMATTR SpiceLine2 GBW=1000Meg
    SYMBOL res -144 672 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R3
    SYMATTR Value 1K
    SYMBOL res 0 672 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R4
    SYMATTR Value 20K
    SYMBOL sw 176 1104 M180
    WINDOW 0 39 71 Left 0
    WINDOW 3 38 46 Left 0
    SYMATTR InstName PWM
    SYMATTR Value COMP
    SYMBOL voltage 112 1072 R0
    WINDOW 0 -102 57 Left 0
    WINDOW 3 -112 64 Invisible 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName RAMP
    SYMATTR Value PULSE(1 5 500n 9.5u 500n 0 10u)
    SYMBOL res 192 816 R180
    WINDOW 0 -34 68 Left 0
    WINDOW 3 -34 44 Left 0
    SYMATTR InstName R6
    SYMATTR Value 1K
    SYMBOL voltage 320 1072 R0
    WINDOW 0 -89 46 Left 0
    WINDOW 3 -88 68 Left 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value 15V
    SYMBOL voltage 672 1072 R0
    WINDOW 0 -82 56 Left 0
    WINDOW 3 24 104 Invisible 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName CLK
    SYMATTR Value PULSE(0 15 0 10n 10n 250n 10u)
    SYMBOL Digital\\inv 752 976 R0
    WINDOW 0 18 98 Left 0
    SYMATTR InstName A2
    SYMATTR SpiceLine Vhigh=15 Vlow=0 Trise=10n Tfall=10n
    SYMBOL Digital\\and 928 704 R0
    SYMATTR InstName A3
    SYMATTR SpiceLine Vhigh=15 Vlow=0 Trise=10n Tfall=10n
    SYMBOL cap 64 672 R90
    WINDOW 0 0 32 VBottom 0
    WINDOW 3 32 32 VTop 0
    SYMATTR InstName C3
    SYMATTR Value 1n
    SYMBOL diode -48 800 R270
    WINDOW 0 32 32 VTop 0
    WINDOW 3 0 32 VBottom 0
    SYMATTR InstName Z1
    SYMATTR Value ZID
    SYMBOL bv -272 816 R180
    WINDOW 0 -34 -49 Left 0
    WINDOW 3 -134 -69 Left 0
    SYMATTR InstName BIVBUS
    SYMATTR Value V=-I(VBUS)*100m
    SYMBOL Digital\\dflop 720 688 R0
    WINDOW 0 49 -16 Left 0
    SYMATTR InstName A4
    SYMATTR SpiceLine Vhigh=15 Vlow=0 Trise=10n Tfall=10n
    SYMBOL Digital\\and 576 736 R0
    SYMATTR InstName A5
    SYMATTR SpiceLine Vhigh=15 Vlow=0 Trise=10n Tfall=10n
    SYMBOL res 304 560 R180
    WINDOW 0 48 62 Left 0
    WINDOW 3 36 40 Left 0
    SYMATTR InstName R2
    SYMATTR Value 3R3
    SYMBOL ind2 -224 320 R270
    WINDOW 0 32 56 VTop 0
    WINDOW 3 5 56 VBottom 0
    SYMATTR InstName LBA
    SYMATTR Value 360µ
    SYMATTR Type ind
    SYMATTR SpiceLine Rser=10m
    SYMBOL res 48 560 R180
    WINDOW 0 49 65 Left 0
    WINDOW 3 36 40 Left 0
    SYMATTR InstName R1
    SYMATTR Value 3R3
    SYMBOL nmos 64 480 R0
    WINDOW 0 -102 -107 Left 0
    WINDOW 3 -104 -83 Left 0
    SYMATTR InstName M1
    SYMATTR Value STW11NM80
    SYMBOL ind2 144 320 R270
    WINDOW 0 32 56 VTop 0
    WINDOW 3 5 56 VBottom 0
    SYMATTR InstName LBB
    SYMATTR Value 18µ
    SYMATTR Type ind
    SYMATTR SpiceLine Rser=1m
    SYMBOL diode 416 320 R270
    WINDOW 0 32 32 VTop 0
    WINDOW 3 0 32 VBottom 0
    SYMATTR InstName DBOOST
    SYMATTR Value DID
    SYMBOL voltage 592 480 R0
    WINDOW 0 38 45 Left 0
    WINDOW 3 38 69 Left 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName VOUT
    SYMATTR Value 400V
    SYMBOL voltage -272 480 R0
    WINDOW 0 39 44 Left 0
    WINDOW 3 39 68 Left 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName VBUS
    SYMATTR Value 100V
    SYMBOL Misc\\nigbt 320 480 R0
    WINDOW 0 57 34 Left 0
    WINDOW 3 58 59 Left 0
    SYMATTR InstName Q1
    SYMATTR Value IRGP50B60PD1
    SYMBOL voltage -272 1072 R0
    WINDOW 0 35 42 Left 0
    WINDOW 3 38 66 Left 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName VIDEM
    SYMATTR Value 2V
    SYMBOL res -144 928 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R5
    SYMATTR Value 1K
    SYMBOL diode 352 336 R0
    SYMATTR InstName D1
    SYMATTR Value DID
    SYMBOL res 704 320 R0
    SYMATTR InstName R7
    SYMATTR Value 0.1
    TEXT -272 1248 Left 0 !.MODEL DID D(RON=10m ROFF=1E6)
    TEXT -272 1224 Left 0 !.MODEL COMP SW(RON=10m ROFF=1E6 VT=0 VH=0m)
    TEXT -272 1272 Left 0 !.MODEL ZID D(RON=10m ROFF=100E6 VFWD=0V VREV=6V)
    TEXT -272 1296 Left 0 !.tran 0 200u 100u 100n uic
    TEXT 392 1224 Left 0 !.lib opamp.sub
    TEXT -80 272 Left 0 !K1 LBA LBB 1
    TEXT 392 1248 Left 0 !.include irgp50b60pmod.spi
     
  3. Genome

    Genome Guest

    OK, it's not complete but the model and a piccy of it is uploaded if you
    wish to play...

    http://www.genomerics.org/patent/patent.html

    If you don't know what's going on

    http://www.genomerics.org/patent/newpfc.html

    If you do....

    Cheers

    DNA
     
  4. Genome

    Genome Guest

    Indeed, the original is a pile of old cobblers. It was really just a quick
    hack as an example of what might be used. You are quite right about leakage
    inductance messing things up and, although the gate drives can be adjusted
    to take care of it, it is a bit of a kluge. The other big problem is the
    variable reverse bias it would apply in a real PFC circuit...... not good.

    I've got a new one

    http://www.genomerics.org/patent/newpfc.html

    This time I've dangled a Forward Converter off the PFC output to generate
    the reverse bias (it's got leakage inductance in it) and this time the level
    is more precisely controlled.

    Cheers

    DNA
     
  5. Robert Baer

    Robert Baer Guest

    Be a little discreet about this...get a little segration here and do
    not use the integrated IGBT.
    The resistor across the EB junction, as "everyone" knows, cannot pull
    out the stored charge fast enough - unless it is so low that it
    dissipates too much power when the device is on.
    So...what to do?
    Use another transistor (NPN) and break that resistor into two resistors.
    The following "trick" is something that i vaguely remember from about
    30 years ago that i had seen only once, so i may have the NPN emitter
    and collector reversed.
    M1 drain to R1, R1 to NPN base and R2, R2 from NPN base to NPN
    collector and PNP base; finally NPN emitter to PNP emitter.
    The NPN is used in the inverted configuration to decrease the on
    voltage drop.
    The NPN turns on only when there is no drive; the stored base charge
    now applies a (divided) drive to the NPN and turns it on, pulling
    current out of the base.
    Pulse current can be a number of amps in a few nanaoseconds and lasts
    a few nanoseconds (during the discharge).
    Impulse power is not too high, but due to the short period of time,
    the duty cycle is extremely low.

    Hope i have not completely messed it up.
     
  6. Robert Baer

    Robert Baer Guest

    Hmm..turn on an inductor, and the current increases; if the incoming
    waveform is a part of a sinewave, then the load can see that sine wave,
    and then at zero, one has the turnoff problem.
    Choices: off at zero current, or off at zero volts; in either case,
    there is a fair amount of power that is going to be dissipated during
    off time.
    So..fi one adds (in series) an LC tank properly tuned, the net result
    may be something a bit closer to having the voltage and current
    waveforms back in sync.
    Be advised, that due to losses in the inductors, that the "ideal"
    tuned frequency is not going to be at 3*f; if i remember right (almost
    40 years) it will be a little lower - and the losses will ensure an
    imperfect match.
    Adding another LC tank in series (roughly 5*f) will help so little
    that the cost of parts and space are normally not worth considering.
    Note the extension of this trick gives one what is called a Gilleman
    (sp?) Line.
     
  7. I notice that the mosfet in the IGBT is turned Off,
    before the -20A applied.

    It might be useful to have a look at keeping the
    mosfet On, apply the -20A, then turn the mosfet Off.
    This sequence holds the base of the pnp at a known
    low impedance 0V whilst its emitter is taken negative.

    Also clamp the IGBT so that the -20A does not take
    it, say, more than 0.7V below 0v. The maximum Veb
    is then defined.

    Hmm... reminiscent of commutating an SCR.
     
  8. James Arthur

    James Arthur Guest

    <snip>

    Genome, color me stupid, but it looks like your model switches off in
    about 200nS, but IRF specs the device to switch in roughly 1/3rd that
    time:

    http://www.irf.com/product-info/datasheets/data/irgp50b60pd.pdf

    Also, IRF specs the max turn-off loss at 530uJ, versus your
    (modelled) 1.56mJ.

    I'm sure I've missed something obvious...kindly bludgeon me with
    enlightenment. (Not that this affects your loss-saving gadget)

    Best,
    James Arthur
     
  9. Genome

    Genome Guest

    In the original setup, on the first page this is the case. That worked for
    the particular arrangement I had at that time and it was the simplest to
    implement. The patent application does mention the fact that relative timing
    of the drive waveforms may need adjusting.

    On the new page, with the new PFC circuit, I had to provide drive waveforms
    that do what you describe to achieve the effect.

    http://www.genomerics.org/patent/newpfc.html

    On the first page the turn off current source is -20.1A so only 100mA is
    available to turn the device off. Clamping the device with a diode would
    mean that you don't provide sufficient reverse bias to remove the stored
    charge.

    'Hmm... reminiscent of commutating an SCR.'

    There was mention of that but I sort of discounted it. I suppose they might
    be concerned that if what I am proposing for an IGBT has already been done
    with SCRs then the patent might not be valid on the grounds of obviousness.
    OTOH if it were so obvious because it is done with SCRs why is it not being
    done with IGBTs?

    Thanks

    DNA
     
  10. Genome

    Genome Guest

    Yes, you are right. However I do make a statement on the first page....

    "Good old LTSpice let's us have a look at the sort of behaviour that makes
    life dull. If you believe the models that is."

    It's one of Wins pet moans about the disagreement between spice models and
    reality. I used the IR model because it does manage to demonstrate the kind
    of behaviour I'm trying to overcome. ST models are/were rubbish in that
    respect showing little to no turn off losses.

    Cheers

    DNA
     
  11. Genome

    Genome Guest

    Errrrm, I'll try harder but, at the moment I can't quite visualise that one.
    However I am trying to improve the behaviour of an IGBT as provided so
    implementing a discrete thing is a step in the wrong(probably right)
    direction.....

    OK..... might have got it. Not too sure about it though.

    Thanks

    DNA
     
  12. Yes ok thanks. A quick Run of newpfc shows that
    the -20A pulse nicely straddles the mosfet drive
    negative-going edge.
    But maybe some means of defining the maximum Veb
    is going to be neccessary?

    A quick glance at the IR data sheet mentioned
    earlier shows that there is some form of body
    diode in an IGBT. Does your model contain that?
    Well, commutation is a generic word. Here you are
    applying a form of commutation to the new and specific
    application of speeding up the turnoff of an IGBT.
     
  13. Genome

    Genome Guest

    Apologies for not doing this in line, never works for me.

    Yes some sort of Oh Shit! protection might be prudent. However the method
    shown in the second circuit does provide a reasonably well defined reverse
    bias level..... Ignoring the ringing.

    I have found a data sheet for a high voltage switching transistor which goes
    as far as specifying a repetitive Veb avalanche energy.... It's probably the
    case that it is permissible to operate many things under such conditions but
    they just haven't been qualified for that mode of operation.

    Yes.... I have commented out the clamp diode from the original model so if
    you downloaded it from the website it's not there.

    As to obviousness or newnesss.... I'm with you on that one. That's to be
    expected but at the level I've seen patents operate it should qualify as
    being valid.... if it really hasn't been done before.


    I've had a look around the interwank for the 'expert' that responded and I
    have found information that causes me some doubts as to wether he is truly
    qualified to give a valued judgement about the method. He seems too far
    removed from the technical guts of things.

    Hmmmmmm, obviously I've got a blinkered view about this.. Either he phoned
    me up to give a company approved whitewash or he phoned me up to blither and
    reported blither to the non-technical side who took his advice and cancelled
    interest.

    Ho hum

    DNA
     
  14. James Arthur

    James Arthur Guest

    Your disclaimer is clear and noted.

    Kundun, I am but a bug, but if you've got a honking FET there
    anyhow, why not parallel it with the IGBT, drive both ON
    simultaneously, and turn the FET OFF a recovery-time after turning off
    the IGBT?

    In this way you'd gain the switching speed of a FET, save some
    switching loss at turn-on too--further improving efficiency--and
    secure the saturation voltage advantages of the IGBT. The FET need
    only handle the full load briefly, and so could be small. Drive would
    be simple.

    Humbly yours,
    James Arthur
     
  15. Well, my approach is to hammer the macromodel until it matches the
    bench measurements (and we're talking about the appropriate bench
    measurements for the design at hand). Then, and only then, am I
    ready to start on Spice circuit trials. Part of this process for
    me is tearing apart various manufacturer's models to see what makes
    them tick. There's also a considerable body of literature on the
    failings of various models and possible solutions. But in several
    cases I've not found any guidance in the literature, and have had
    to roll out my own workarounds.

    Having done all this you can begin to have some confidence in the
    circuit modeling. Afterwhich it's back to the bench for some
    full-circuit comparisons.
     
  16. Genome

    Genome Guest

    The grovelling is unecessary.... I am not Welsh so my first name is not Dai.

    Yes, what you suggest was in my journey to the final answer. The second
    circuit on the first page shows something that would be similar. The I2
    current source reduces the IGBT current to zero in the same way a directly
    paralleled mosfet would.

    However, as suggested, the problem is stored charge. The recovery time you
    mention is the time for charge recombination to occur. I do not know much
    about this process other than some words for it. However it takes a
    relatively long time if left to its own devices. There are processing
    methods and such stuff that reduce this called names like lifetime killing
    or quenching but they still don't seem to work too well.

    I suppose that if you are prepared to sit around waiting for it to happen
    then it does work but that is going to be a long and variable time.

    This is why I thought about actively removing the charge by applying a
    reverse bias to the device. This is done in transistor switching ciruits and
    is easy because the base terminal is available. With the IGBT it is not but
    by dangling stuff about the place it is possible to get the mosfet to do the
    job.

    In the first boost circuit that is done by splitting the boost inductor.
    That's a bit loose. In the second circuit, on the second page, it is done by
    adding the forward converter part which produces a more tightly defined
    result.

    When I had done it I hunted around for patents that did the same thing. I
    found many that use a simple paralleled mosfet, which does not work very
    well as far as I am concerned. I did not find any that applied a reverse
    bias.... which does work exceptionally well.

    There's all sorts of stuff about the relative timing and length of drives
    and selection of devices and possibilities for zero voltage switching that
    make things a bit more complicated.

    By having a fiddle in the circuit on the second page I can get the
    'parallel' mosfet losses down to 3W. The IGBT loses about 29W and the mosfet
    that does resonant switching of the diode, and other bits, loses 23W. If I
    put a SiC diode in there I might get rid of those 23W so total losses for a
    2kW PFC stage would be 32W.

    Take those figures with a big pinch of salt though.

    DNA
     
  17. Genome

    Genome Guest

    If I was clever I might force myself to do the same. No, not really.
    Unfortunately I wouldn't have the patience or environment to do the job
    properly. I'll still use them to gain a basic idea about what to expect
    prior to building something and then see what the 'real' results are.

    I did check model behaviour against the dirty sheet to confirm that things
    sort of behaved in a similar way. I was just after a 'proof' of concept. I'm
    still not certain that the modelling really does prove the concept but it
    has a feel to it.

    So..... since your here I'm bound to ask.... What do you think of the idea?

    Cheers

    DNA
     
  18. James Arthur

    James Arthur Guest

    Genome, if I've made you blush, my mission on Earth is complete.
    And you, one of sed's randiest. Now I can die contented.

    That is the question--how long is "very long?" There's no doubt
    that sucking the charge out will speed things up over simply letting
    it decay. Being IGnorant of IGBTs, I'm counting on Mother IRF's
    datasheet not being a giant lie when they say the turn-off time is
    thus-and-so. Generally, typical fall time for i(c) is <60nS from 20-
    to-50 amps.

    If that were true, and one didn't mind the wait, then one could just
    wait those 60nS out, MOSFET 'on.'

    Otherwise, if you're insistent on rushing your electrons hither and
    yon, then back again quickly, then your gizmo is very nice, of course.

    Best,
    James Arthur
     
  19. Genome

    Genome Guest

    You are making powerful arguments to someone who is equally uncertain about
    what is really going on, certainly more powerful than others I have heard.
    Ultimately I suppose I'm going to have to do it and see if it is really
    worth having.

    Hmmmmm worry, worry ,worry.

    There you go, now you can die more than contented.

    DNA
     
  20. <http://www.techonline.com/article/192200366>

    On Fig.12 the FET On-time straddles the IGBT Off-going.
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-