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Transistor matching issue

M

Michele Ancis

Jan 1, 1970
0
Hi all,

I have a matching problem, maybe somebody here can give me a hint. I have a
low noise Hetero Junction FET (NEC3210S01), I would like to match it for
optimum return loss, not for optimum noise. I've therefore calculated the
input and output loads to be presented to my transistor for simultaneous
conjugate match. The transistor must be matched from 9 to 10 GHz, so we're
talking about a 10% bandwidth, not narrow, not broad.

Moreover, the matching networks should be as simple as possible: I would
need the networks to introduce as little phase shift across the band as
possible. That is, I can't afford having multiple matching stages, as it
would for sure broaden my matching but also introduce an unwanted phase
shift. Of course we're talking about distributed networks, microstrip on a
Rogers 4003 0.5mm subsrate. What I have, from the optimization, is that I
can't get any better than -10 dB input return loss at the edges of the
band, while the output matching is OK. I would be fine with -15dB at the
input as well...;-)

While investigating the behaviour of my "optimum" input gamma, that is how
my generator should look like, I found an interesting thing about which I'd
like to hear from someone more experienced. "Normal" impedances follow a
clockwise path in the Smith chart, when going from low to higher freq. In
other words, the phase slope of "normal" impedances is negative. The only
way to produce a positive phase slope is being in the neighborhood of a
zero...However, since the conjugate input gamma is, roughly, conj(S11), one
has that the optimum impedance he should synthesize is something going the
other way...counter-clockwise with frequency. This is because the optimum
gamma is - roughly - the conjugate of the input gamma, which being "normal"
goes clockwise...
I would be interested to hear from anybody who has "observed" this thing
and maybe thought about it...

Finally, being constrained not to use multiple sections, a possible
approach would be to use some feedback and maybe loose a bit in gain, which
I could afford, for an "easier" input matching...Pity I haven't the
foggiest idea how to properly feed back my transistor, given that I can't
use lumped elements at 10 GHz (maybe resistors, but how? I don't want to
destroy my NF)...Again, any insight or idea would be greatly appreciated...

Thank you in advance,

Michele
 
M

Michele Ancis

Jan 1, 1970
0
In data Mon, 16 Feb 2004 16:44:09 GMT, maxfoo ha scritto:
Why are you wasting your time matching that crappy fet when you can buy
a mmic already matched?

http://www.hittite.com/index.cfm?bo...mplifier&catid=1&sort=function&source=leftnav
Thanks Max, I know Hittite and believe me, there are still some situations
where you must resort to discrete. Nevertheless, it's not my intent to
convince you of that...As I said, I have a specific problem. Have you got
any REAL hint about that?

Thanks,

M
 
G

Gilbert Mouget

Jan 1, 1970
0
dated Mon, 16 Feb 2004 16:41:18 +0100,
The transistor must be matched from 9 to 10 GHz, so we're
talking about a 10% bandwidth, not narrow, not broad.

Moreover, the matching networks should be as simple as possible: I would
need the networks to introduce as little phase shift across the band as
possible. That is, I can't afford having multiple matching stages, as it
would for sure broaden my matching but also introduce an unwanted phase
shift. Of course we're talking about distributed networks, microstrip on a
Rogers 4003 0.5mm subsrate. What I have, from the optimization, is that I
can't get any better than -10 dB input return loss at the edges of the
band, while the output matching is OK. I would be fine with -15dB at the
input as well...;-)

While investigating the behaviour of my "optimum" input gamma, that is how
my generator should look like, I found an interesting thing about which I'd
like to hear from someone more experienced. "Normal" impedances follow a
clockwise path in the Smith chart, when going from low to higher freq. In
other words, the phase slope of "normal" impedances is negative. The only
way to produce a positive phase slope is being in the neighborhood of a
zero...However, since the conjugate input gamma is, roughly, conj(S11), one
has that the optimum impedance he should synthesize is something going the
other way...counter-clockwise with frequency. This is because the optimum
gamma is - roughly - the conjugate of the input gamma, which being "normal"
goes clockwise...
I would be interested to hear from anybody who has "observed" this thing
and maybe thought about it...

Yes, Foster's theorem and simulating a negative capacitance for
broadband matching...

You need a CAD tool like Puff or Agilent EEsof EDA in order to play
with series or shunt stubs.

See for instance :
www-cad.eecs.berkeley.edu/~dluca/ ee217/Broadband_LNA_report.pdf


Finally, being constrained not to use multiple sections, a possible
approach would be to use some feedback and maybe loose a bit in gain, which
I could afford, for an "easier" input matching...Pity I haven't the
foggiest idea how to properly feed back my transistor, given that I can't
use lumped elements at 10 GHz (maybe resistors, but how? I don't want to
destroy my NF)...Again, any insight or idea would be greatly appreciated...

Inductive source feedback, but at 10GHz we are talking two very very
short lines...
 
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