Traffic Light Project

[vick5821]

http://www.kpsec.freeuk.com/projects/trafficlight.htm

Referring to this circuit, the 555 will send a pulse to the 4017 clock pin when the output pin(pin 3) is HIGH ?

 

[(*steve*)]

Check the datasheet for the 4017.

The clock input is sensitive to transitions, not levels.

Depending on the input you use it is either the rising (pin 14) or falling (pin 13) edge that does the business.

And that circuit uses pin 14...

 

[vick5821]

Check the datasheet for the 4017.

The clock input is sensitive to transitions, not levels.

Depending on the input you use it is either the rising (pin 14) or falling (pin 13) edge that does the business.

And that circuit uses pin 14...

Further explanation ? What business you mean ?

 

[(*steve*)]

the business I refer to is the function that the 4017 performs, i.e. the stepping through the states of a Johnson counter.

The 4017 does not do anything when the clock input(s) are high or low. It does it's stuff, it's business, it's magic, it's changing of state (etc.) on the rising edge of the clock pulse (on pin 14) *or* the falling edge on pin 13.

Rising edges are the transition from a low (logic 0) state to a high (logic(1) state. Falling edges are the transition from 1 to 0 (high to low).

You will generally find that devices with clock inputs have functions that are synchronous and those which are asynchronous. Synchronous functions occur on a clock transition, and asynchronous activities occur regardless of clock state or transition.

An example is the normal counting of the 4017. It is synchronous with the clock and occurs on the rising/falling edges of the clock pulse as detailed above.

An example of an asynchronous function is the clear of the 4017. In addition to this being asynchronous (i.e. it clears the counter immediately, not on receipt of the next clock transition) it is also level sensitive. The device remains in the cleared state while the MR (pin 15) remains high.

Knowing and understanding the difference is important and will make it obvious that the mark/space ratio of the clock pulse is relatively insignificant, however the time the MR signal remains asserted is.

 

[vick5821]

the business I refer to is the function that the 4017 performs, i.e. the stepping through the states of a Johnson counter.

The 4017 does not do anything when the clock input(s) are high or low. It does it's stuff, it's business, it's magic, it's changing of state (etc.) on the rising edge of the clock pulse (on pin 14) *or* the falling edge on pin 13.

Rising edges are the transition from a low (logic 0) state to a high (logic(1) state. Falling edges are the transition from 1 to 0 (high to low).

You will generally find that devices with clock inputs have functions that are synchronous and those which are asynchronous. Synchronous functions occur on a clock transition, and asynchronous activities occur regardless of clock state or transition.

An example is the normal counting of the 4017. It is synchronous with the clock and occurs on the rising/falling edges of the clock pulse as detailed above.

An example of an asynchronous function is the clear of the 4017. In addition to this being asynchronous (i.e. it clears the counter immediately, not on receipt of the next clock transition) it is also level sensitive. The device remains in the cleared state while the MR (pin 15) remains high.

Knowing and understanding the difference is important and will make it obvious that the mark/space ratio of the clock pulse is relatively insignificant, however the time the MR signal remains asserted is.

Then how do I activate so as to make the 4017 function ?

 

[(*steve*)]

You use the 555 just as it is in the circuit diagram.

There is nothing special to the 4017 of the output of the 555 being high. It is the transition from low to high (on the pin you're using) that does stuff inside the 4017.

Your original question

Referring to this circuit, the 555 will send a pulse to the 4017 clock pin when the output pin(pin 3) is HIGH ?

has the strict answer "no" because it is the output pin of the 555 transitioning from low to high (not being high) which clocks the 4017.

Furthermore, a clock pulse is (generally speaking) the transition from logic 0 to logic 1, then back to logic 0. this is the output of the 555 going from low to high, then high to low -- clearly this cannot happen *while* the output of the 555 is high.

 

[vick5821]

You use the 555 just as it is in the circuit diagram.

There is nothing special to the 4017 of the output of the 555 being high. It is the transition from low to high (on the pin you're using) that does stuff inside the 4017.

Your original question

Oh..The clock input of 4017 need a clock pulse which means that when the output of 555 going from LOW to HIGH then LOW, this is consider as ONE clock pulse ?

has the strict answer "no" because it is the output pin of the 555 transitioning from low to high (not being high) which clocks the 4017.

Furthermore, a clock pulse is (generally speaking) the transition from logic 0 to logic 1, then back to logic 0. this is the output of the 555 going from low to high, then high to low -- clearly this cannot happen *while* the output of the 555 is high.

Oh, so a clock pulse is needed for the clock pin of 4017. This means that LOW --> HIGH -- >LOW and this is consider as one clock pulse ? which make the LED connected to Q0 lights up ? then when will it off ? when it enter second clock pulse ?

 

[(*steve*)]

As wired it is the rising edge of that clock pulse that causes the 4017 to do it's stuff. Id doesn't change state until another rising edge comes along.

After a reset, Q0 is high. So after one rising edge, Q0 goes low, and Q1 goes high.

Then the next rising edge causes Q2 to go high and Q1 to go low, and so on...

 

[vick5821]

As wired it is the rising edge of that clock pulse that causes the 4017 to do it's stuff. Id doesn't change state until another rising edge comes along.

After a reset, Q0 is high. So after one rising edge, Q0 goes low, and Q1 goes high.

Then the next rising edge causes Q2 to go high and Q1 to go low, and so on...

How do I know whether it is rising edge or failing edge ? Any hint ? LOL

 

[(*steve*)]

Do you know the difference between going up a step and going down a step?

 

[vick5821]

Do you know the difference between going up a step and going down a step?

Yes..I know..rising edge is going up a step while falling edge is going down a step right ??

 

[(*steve*)]

Yep. That's right.

Your oscillator gives low, rising edge, high, falling edge, low, rising edge, high, falling edge, ..

And the 4017 responds (i.e does something) exactly once in each clock cycle... That point is during the rising edge of the clock .

 

[vick5821]

Yep. That's right.

Your oscillator gives low, rising edge, high, falling edge, low, rising edge, high, falling edge, ..

And the 4017 responds (i.e does something) exactly once in each clock cycle... That point is during the rising edge of the clock .

How do I determine this from the circuit ?

 

[(*steve*)]

You don't.

You determine it from the datasheets of the 555 and the 4017. And from a basic understanding of digital logic.

The understanding is probably a little beyond high school science, but I'd say well within what you'd learn in your first semester of an appropriate University course.

If you're not yet anywhere near uni, don't stress. The knowledge is pretty trivial.

You need to understand basic logic gates, then the SR flip flop, then a clocked flip flop.

From that you can develop an understanding of most logic because you will understand edge triggering (from the SR flip flop) and clock signals (from the JK flip flop).

Alternatively you could just study the datasheet, looking at the various truth tables and other representations of what the 4017 does.

You need to be able to understand the abstraction and then you can ignore it (the details) and move on to something more complex.

 

[vick5821]

You don't.

You determine it from the datasheets of the 555 and the 4017. And from a basic understanding of digital logic.

The understanding is probably a little beyond high school science, but I'd say well within what you'd learn in your first semester of an appropriate University course.

If you're not yet anywhere near uni, don't stress. The knowledge is pretty trivial.

You need to understand basic logic gates, then the SR flip flop, then a clocked flip flop.

From that you can develop an understanding of most logic because you will understand edge triggering (from the SR flip flop) and clock signals (from the JK flip flop).

Alternatively you could just study the datasheet, looking at the various truth tables and other representations of what the 4017 does.

You need to be able to understand the abstraction and then you can ignore it (the details) and move on to something more complex.

I am in the university level now and currently now learning digital fundamentals. Could you roughly explain about it so that I get rough idea ?

 

[(*steve*)]

You need to review your understanding of flip flops (I hope you're OK up to that)

Understand the basic SR flip flop and what causes it to change state and what happens in other states (i.e. mostly *nothing*)

Then review whatever you covered about clocked logic, what clock pulses are, etc.

It's really the basic stuff and if you didn't understand that, it is no wonder you're having trouble.

Perhaps look at this and this. They're not the best, but you should understand this stuff -- It should be second nature. If it's not, keep studying the basics until it is.

 

[vick5821]

You need to review your understanding of flip flops (I hope you're OK up to that)

Understand the basic SR flip flop and what causes it to change state and what happens in other states (i.e. mostly *nothing*)

Then review whatever you covered about clocked logic, what clock pulses are, etc.

It's really the basic stuff and if you didn't understand that, it is no wonder you're having trouble.

Perhaps look at this and this. They're not the best, but you should understand this stuff -- It should be second nature. If it's not, keep studying the basics until it is.

Ok.Thank you..I will study more about it.

Thank you..So after reviewing that, I am able to determine whether the circuit I constructed is rising edge or falling egde is it ? Is this the outcome ?

Thank you

 

[(*steve*)]

No, after understanding that you will understand (hopefully) enough about digital electronics to be able to understand why your questions are not making any sense.

That latter video doesn't explain the JK flip flop very well, look in your text -- it should be described there. You need to understand how a clock signal initiates a single action, and that the action is initiated on the edge of the clock pulse.

I would recommend "The Art of Electronics" section 8.17 (the first half) pp 507 to 509

 

[vick5821]

No, after understanding that you will understand (hopefully) enough about digital electronics to be able to understand why your questions are not making any sense.

That latter video doesn't explain the JK flip flop very well, look in your text -- it should be described there. You need to understand how a clock signal initiates a single action, and that the action is initiated on the edge of the clock pulse.

I would recommend "The Art of Electronics" section 8.17 (the first half) pp 507 to 509

I do not have the book ..any ebook available ?

 

[(*steve*)]

What is your text?