After downloading your image, copying, and overlaying it seems that
the two patterns do NOT lie on top each other, rather form small
loops. *IF* there is a gnd plane between, doesn't matter if they
overlay or not. They do appear to be the same length of run and do
appear to have a 'guard trace' along each side. But either the vias
are super tiny which doesn't appear to be the case since vias can be
seen in adjacent areas, or those guard traces are floating.
The two sets of pads, SIM1 and SIM2, look like either simply
mechanical access points. If you took an instrument like a network
analyzer with small pointy tips, it looks possible to touch SIM1 &
SIM2 from either side; which would allow you to measure the
transmission line characteristics of both the outside layer processes
and check/control the PCB manufacturing. That's my vote. Although
we've always laid the test traces nearer to the outside, unused areas
of the PCB and therefore the traces were straight.
Just as a note, the vias in that adjacent area look VERY close
together which would cause the power/GND planes to have large holes
cut into them rather than a series of small holes. -- Usually
considered not good for signal integrity AND especially EMC issues.
Did anybody find out what that chip, ASMEDIA ASM1083 does?
...
