R
Raveninghorde
- Jan 1, 1970
- 0
Up to now I have stuck to 2 layer boards.
I've been working on a sepic converter, 10-32V in 4-18V, 0-1A out for
a while. I have had problems resolving the conflict of needing a large
open design so that I have enough copper for heatsinking fets and
diodes and a compact design so as to keep high frequency loops small
for good EMC.
On the latest prototype I've got enough vias and bottom side copper
connected to the drain of the switching fet to keep it cool but this
has taken a chunk out of the ground plane.
So I plan to go to 4 layer on the next version. Top for components,
top and bottom for signal tracks and copper areas for heatsinking, a
middle layer for ground plane and the other middle layer for power,
24V and 5V supplies.
My question is what is good practice for a grid of thermal vias to get
maximum heat transfer from top to bottom layer without compromising
the internal ground plane?
I've been working on a sepic converter, 10-32V in 4-18V, 0-1A out for
a while. I have had problems resolving the conflict of needing a large
open design so that I have enough copper for heatsinking fets and
diodes and a compact design so as to keep high frequency loops small
for good EMC.
On the latest prototype I've got enough vias and bottom side copper
connected to the drain of the switching fet to keep it cool but this
has taken a chunk out of the ground plane.
So I plan to go to 4 layer on the next version. Top for components,
top and bottom for signal tracks and copper areas for heatsinking, a
middle layer for ground plane and the other middle layer for power,
24V and 5V supplies.
My question is what is good practice for a grid of thermal vias to get
maximum heat transfer from top to bottom layer without compromising
the internal ground plane?
