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Thermal capacity of semiconductors / Peak load

Discussion in 'Electronic Design' started by Christian Walter, Apr 10, 2008.

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  1. Hello,

    I just came across an interesting chapter about temperature control in
    one of my books about transient thermal impedance (power electronics -
    converters, applications and design). A device is not only assigned a
    thermal resistance but furthermore also a thermal capacity. I wanted to
    use this for calculating the maximum time I can temporarily overload a
    semiconductor without any cooling. Sadly the manufactures do not supply
    these values.

    Therefore I wanted to ask if somebody has such values for common
    semiconductor packages (e.g. sot-223) and certain device families. Of
    course for some semiconductors typically used for switching the
    manufacture provides such values or you can use the average power. But
    this does not apply for peak pules with a long delay between them.

    Regards,
    Christian
     
  2. Guest

    Win Hill has certainly talked about this here, and may be able to come
    up with some ball-park figures.

    Some semiconductor data sheets do give thermal derating curves as a
    function of the duration of the overload, and these can be translated
    into heat capacity figures. The heat capacity does change with the
    duration of the thermal pulse - for infinitesimal impulses the heat
    capacity is just that of the conducting channel itself, but over
    microseconds the channel substrate comes into the picture, and over
    longer periods the whole package has a chance to warm up.
     
  3. JosephKK

    JosephKK Guest

    Actually that used to be encoded in the safe operating area (SOA)
    curves. Specific data never was provided. If you are good enough, i
    suppose you could approximate it from device dimensions and
    thermodynamics.
     
  4. gearhead

    gearhead Guest

    I paste a typical sample of Winfield Hill thermal analysis hereunder,
    from a Jan 2005 post. You can find the whole thread using Google
    Groups' advanced search function.


    A logic-level FET is a good choice if one wants to use the FET's
    transconductance to establish a constant current electronic load.
    An IRL3716 would be a good choice for a 100A load, because 100A is
    close to the current at which it has zero transconductance tempco,
    with about a 2.9V gate voltage for Vds = 15V, see fig 3. I'd add
    a source degeneration resistor to better establish the current at
    different drain voltages. For example, a 0.02-ohm low-inductance
    resistor would drop 2V at 100A, and a 5.0V gate drive would bias
    the IRL3716 to sink about 90A for 8V to 100A for 15V on the drain.
    One can adjust the gate pulse voltage to trim the 100A current.

    These FETs may be hard to get in the TO-220 version (the surface-
    mount versions, which have less thermal capability, are in stock),
    so an IRF IRL1404 or IRL2505 (Vgs = 3.8V), or a Fairchild FDP7045L
    (Vgs = 3.3V) can be considered instead.


    Done this way, with the battery current dissipated mostly in the
    FET,
    each battery-test pulse has to be short, limited by the thermal mass
    of the MOSFET. The thermal mass parameter isn't given directly on
    the datasheet, but for a quick part search one can eyeball the FET's
    maximum Pd spec, which is usually on the front page. A low thermal
    resistance is required for a high Pd, and this usually implies a
    high
    thermal mass. To complete the calculation for the selected FET, one
    refers to the Maximum Effective Transient Thermal Impedance curves,
    e.g., fig 11 for the IRL3716. For example, let's assume our FET has
    about 10V across its D-S terminals during our 100A pulse, which
    would
    be 1kW dissipation. Assuming a 150C junction temp rise, we
    calculate
    a maximum allowed Thermal Response ZthJC = dT/P = 150C/1kW = 0.15C/
    W,
    and examining the single pulse curve, we see that this corresponds
    to
    a maximum pulse duration of about 500us. This is consistent with
    the
    figure 8 Maximum Safe Operating Area plots.



    Right, we're talking Ciss into the 5nF territory, which requires a
    0.25A gate current for a 0.1us switching time (for a 5V pulse). A
    wimpy 10mA gate-drive capability, as from a CMOS 555 timer, could
    result in a rather slow 2.5us to 5us switching time. That's 1 to 2%
    of a say 250us test pulse.
     
  5. neon

    neon

    1,325
    0
    Oct 21, 2006
    all diodes at some point do go trough a zero temperature coeficient no drift. however the power required to get there needs supplemental cooling. all diodes also no matter what are capable to conduct extreme current but not stady state. current do not destroy a diode but the heat does. so how can you specify a 2n525 to carry 5 amperes if need be for a very short time non repeatetive. So spcify the max current at sustainable power. then it is up to you to pulse it a nano second at 5 amperes.
     
  6. Guest

    Jim Thompson is reliably out of touch with reality, but this unusually
    unrealistic, even for him.
    Just for the record, Fred Bloggs may have his problems, but stupidity
    isn't any of them.
    A question one might also direct at Jim, if one didn't know what the
    answer was going to be.
     
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