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Test patterns- self-adaptive methods

Discussion in 'Electronic Design' started by vlsi99, May 30, 2007.

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  1. vlsi99

    vlsi99 Guest

    A bus interface is an output only from a chip at 50 MHZ , 3.3V
    LVTTL. The target unit receives this data. I heard of some methods
    used to adjust voltage thresholds and timing on the target based on a
    comparison of specific test patterns. If the test patterns fails,
    adjustments to thresholds on timing are made until the comparison is a
    match.
    The bus signals need to get to an FPGA in the target. Specifically in
    hardware, what techniques have people used to accomplish this ? Can it
    be done directly in the FPGA or should it be some special buffer or
    analog circuit to make this adjustments?

    thank you

    Paul
     
  2. John Larkin

    John Larkin Guest

    WShy isn't a direct LVTTL connection reliable? Why would thresholds or
    timing need tweaking? If it's flakey, it should be fixed, not tweaked.
    50 MHz is *slow*.

    John
     
  3. vlsi99

    vlsi99 Guest

    The bus signals goes through PCB1-->Ribbon cable-->PCB2--->Ribbon
    cable--->Target.

    I am just heard that other hardware used in this project have
    implemented this kind of adaptive mechanism as a backup plan in case
    there is problems with the signals.

    thanks

    Paul
     
  4. joseph2k

    joseph2k Guest

    As a comparison idea consider ata133 / eide133 supported by most all recent
    computers without any adjusters. See also PCI bus at 33 and 66 MHz.
     
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