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Taking slow signal rise-times into account when driving a CMOS

Hello,

We have a circuit that generates signals with an extremely slow
rise/fall time (milliseconds). This circuit should feed a digital
IO sampler that has a CMOS input (AHCT245/645...), and it's known
that slow rise/fall times are bad for CMOSes (forcing them to spend
long time in a conducting state, thus generating power and heat
that may cause damage).

The common solution for this problem is placing a shcmidt trigger
(74VHC14) on the circuit's output, to feed a fast signal to the CMOS.

However, one engineer presented the following appnote: "Implications of
Slow or Floating CMOS Inputs"
(http://focus.ti.com/lit/an/scba004c/scba004c.pdf) and claims that this
article doesn't mention that Schmidts themselves don't suffer from the
slow input problem, and that a Schmidt may be damaged from inputs as
slow as 1 ms. He proposes to use a comparator (that has hystheresis) as
the most robust design. On the contrary, many people say that the
Schmidt is enough, and 74VHC14'th data sheet poses no limit on the rise
time.

What is your opinion ? It's an important subject that surely raises
in many designs.

Eli
 
P

Paul Burke

Jan 1, 1970
0
Hello,

We have a circuit that generates signals with an extremely slow
rise/fall time (milliseconds). This circuit should feed a digital
IO sampler that has a CMOS input (AHCT245/645...), and it's known
that slow rise/fall times are bad for CMOSes (forcing them to spend
long time in a conducting state, thus generating power and heat
that may cause damage).

The common solution for this problem is placing a shcmidt trigger
(74VHC14) on the circuit's output, to feed a fast signal to the CMOS.

However, one engineer presented the following appnote: "Implications of
Slow or Floating CMOS Inputs"
(http://focus.ti.com/lit/an/scba004c/scba004c.pdf) and claims that this
article doesn't mention that Schmidts themselves don't suffer from the
slow input problem, and that a Schmidt may be damaged from inputs as
slow as 1 ms. He proposes to use a comparator (that has hystheresis) as
the most robust design. On the contrary, many people say that the
Schmidt is enough, and 74VHC14'th data sheet poses no limit on the rise
time.

The HC14 at 5V has a typical maximum current draw (per gate) of about
500uA at 5V supply, with the input at the worst point in the transition
region. HCTs are worse by about 3x. You'll thus be dissipating an extra
(over the quiescent) 15mW if all 6 inputs are simultaneously at this
black spot, or 50mW say for HCTs. Shouldn't break the bank.

Paul Burke
 
Thanks for the reply, Paul.

Where is the data (voltages, currents) you are stating
from ? We've been unable to find such detailed information about the
operation of the HC14. Alternatively, do you know if it's possible to
see its schematic ?

Eli
 
J

John Larkin

Jan 1, 1970
0
Hello,

We have a circuit that generates signals with an extremely slow
rise/fall time (milliseconds). This circuit should feed a digital
IO sampler that has a CMOS input (AHCT245/645...), and it's known
that slow rise/fall times are bad for CMOSes (forcing them to spend
long time in a conducting state, thus generating power and heat
that may cause damage).

The common solution for this problem is placing a shcmidt trigger
(74VHC14) on the circuit's output, to feed a fast signal to the CMOS.

However, one engineer presented the following appnote: "Implications of
Slow or Floating CMOS Inputs"
(http://focus.ti.com/lit/an/scba004c/scba004c.pdf) and claims that this
article doesn't mention that Schmidts themselves don't suffer from the
slow input problem, and that a Schmidt may be damaged from inputs as
slow as 1 ms. He proposes to use a comparator (that has hystheresis) as
the most robust design. On the contrary, many people say that the
Schmidt is enough, and 74VHC14'th data sheet poses no limit on the rise
time.

What is your opinion ? It's an important subject that surely raises
in many designs.

My opinion: don't worry about it. The input fets are small and the
brief crossover power dissipation won't damage the chips. The TI
appnote showed only 4 mA shoot-through (not sure for which part,
exactly) and had to conjecture 36 continuous overlaps in one part to
demonstrate damage.

And the idea that a Schmitt gate will be damaged by a slow edge
presumes that the designers are total idiots. Or something.

John
 
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