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TAC question, plus CPLD's in Oz

Discussion in 'Electronic Design' started by Michael Brown, Apr 1, 2007.

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  1. I'm slowly moving forward on my frequency counter design (simple counter +
    TAC for partial cycles, giving one readout per second). I've decided to go
    with a CPLD coupled with an ADC, currently looking at a XC9572XL and an
    ADCS7476 respectively. I've taught myself enough Verilog to get a working
    design using ISE Webkit - I use a serial protocol used for getting timing
    information and firing calibration events, and passing through the results
    from the ADC. All in all requires very few external components.

    I have two questions, the first regarding the TAC part. First is whether I
    should use a constant current source or a constant voltage source to charge
    the capacitor. The nonlinearaties from the constant voltage source can be
    dealth with through postprocessing by the microcontroller (which needs to be
    done anyhow), and high-stability constant voltage sources are easy to
    acquire. A constant current source would AFAIK be significantly more
    complex. However I may be missing something - is it actually rather easy to
    build a stable constant current source?

    The basic schematic looks like:
    VConst
    |
    |
    /
    Start -----|
    \
    |
    |
    |
    |
    /
    Stop -----|
    \
    |
    |
    |-------- To ADC
    |
    ---
    ---
    |
    |
    |
    GND

    Both transistors being NPN. Stop is initially held high, and Start is
    brought high at the start of the measurement period. At the end of the
    measurement period, Stop is brought low. Soon afterwards, the ADC
    measurement is made. After the ADC measurement, Start is brought low and
    Stop is brought high again. The time between the start and stop pulses is
    anywhere from 0 to 375 ns, and the time between the stop pule and the next
    start pulse is in the order of 200 ms. I went for this dual-transistor
    layout with the intention of tuning the Start transistor for a sharp rising
    edge and the Stop transistor for a sharp falling edge. However, I'm not
    exactly sure of the best way to do either of these :) For the falling edge,
    I was guessing that I would hold the transistor just outside of saturation,
    then use the stop signal (through another transistor) to yank the base to
    ground as fast as possible. However, would this generate a noisy voltage
    drop across the Stop transistor? I couldn't find much information on
    increasing rising edge performance, so any tips/links regarding this would
    be appreciated. Alternatively, if there's some other topology that is
    better, I'm open to suggestions.

    The second main question is with regards to sourcing parts. The only
    Australia-local source for CPLDs that I can find is RS components, who sell
    them at insanely high prices compared to what they cost from US stores. Are
    there any places in Australia who charge reasonable prices for CPLDs, or is
    it worthwhile to simply to batch things up and do an order from Digikey?
     
  2. Chris Jones

    Chris Jones Guest

    Have you considered using reciprocal counting for low frequencies, or a
    mixture of simple counting and reciprocal counting?

    For example, you could wait for an edge of the input waveform, then start
    two counters, one clocked by the unknown frequency and the other one
    clocked by a 10MHz reference clock. When the reference counter reaches
    500ms, then wait for the next edge of the unknown frequency and then freeze
    both counters. You now have one counter that gives a time period of at
    least 500ms known to within about +/- 2/10MHz = 200ns, which gives a good
    approximation of the time duration of an integer number of cycles of the
    unknown frequency (that integer is held in the other counter). This should
    give you better than 1ppm of error contribution due to the counting process
    without bothering with analogue circuitry, and it should work for unknown
    input frequencies up to at least tens of MHz. For even less error in the
    timing, a high than 10MHz clock could be used, especially with modern
    FPGAs.

    Does anyone have any simple improvements on this scheme?

    Chris
     
  3. Unfortunately, 1 ppm is not quite enough ... I'm aiming to measure crystal
    frequency drift (using a rubidium reference 1 PPS source, though it probably
    has other frequency outputs), so would ideally like something around the
    1E-8 level (0.01 ppm), which would require in the order of a 100 MHz clock.
    At that speed, my attempts at digital electronics become rather analogue
    again ;)

    While it wouldn't be impossible to refine things enough to run at much
    higher clock rates, the TAC approach seems (to me) to be the easier way out,
    albeit requiring a bit of hand tuning to get it working right. Additionally,
    it should scale up nicely if I plan on increasing the frequency that I'm
    measuring, hopefully always netting an order of magnitude or more gain in
    resolution over simple cycle counting. The main thing holding it back would
    be the start/stop switching, which could get messy at higher speeds.

    [...]
     
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