# Synchronous Counter Circuit with "mystery output."

Discussion in 'General Electronics Discussion' started by jdouglasusn, Aug 7, 2012.

1. ### gorgon

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Jun 6, 2011
You should put a capacitor of some uF, like 47-100uF on the 5V supply entry, and a 100nF over each chip's supply pins. The 7805 regulator need a capacitor on the output, and the large capacitor will serve as a reservoir for powerspikes from the LSTTL chips. The 100nF will remove the high frequency noise induced on the power lines, or at least reduce it.

TOK

2. ### jdouglasusn

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May 29, 2012
ah, I see. Thanks

I also googled a 555 timer, and when I hook it up, it doesn't change a thing either.
I'm using R1 = 2.2k, R2 = 4.7k, and C1 = 10uF

Since the circuit act on a negative going pulse, should I make the duty cycle >50% ?

3. ### jdouglasusn

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0
May 29, 2012
I did some tweeking,

Everything works fine now. Thanks a bunch for your help.

4. ### donkey

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Feb 26, 2011
I wouldn't feel dumb if I were you.... I am still googling what a synchronous counter is.... seriously

5. ### Harald KappModeratorModerator

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Nov 17, 2011
@donkey:
You have basically two ways of constructing a counter:
1) asynchronous
2) synchronous

Regardless of this distinction a counter operates by cycling a set of flipflops through a defined set of states. Each state is a unique "count". A simple technique is using the binary number system to mark the states and at the same time output the count, e.g. 0001, 0010, 0011 etc. Others are possible (e.g. a Johnson counter as used in the 4017 CMOS IC).

The difference between synchronous and asynchronous is the way the counter advances from one state to the next:

In a synchronous counter every flipflop is connected to the same clock input. The state of a flipflop is determined from the previous stae of all other flipflops.
The advantage is that all outputs change at the same time (in reaqction to the active clock edge, give or take a few nanoseconds for tolerances in propagation delay).
The disadvantage is that the clock line is loaded by many clock inputs (which may require strong clock drivers) and that the logic for decoding the next stage may become quite complex the longer the counter becomes.

In an asynchronous counter the clock input fpr each flipflop is derived from the output of the other flipflops. Only the first flipflop is triggered by the external clock source.
The advantage of this circuit is that the clock line is very little loaded and that the logic to decode the next state from the previous state can be very simple.
The disadvantage is that the otputs of the flipflops change asynchronously. First the flipflop triggered by the external clock changes state. This change of state triggers the change of the next flipflop and so on. The outputs show a rippling count. This is especially undesired if the flipflop's outputs (the count) are used by a decoding circuit: during the ripple phase the counter shows false outputs. Only after the ripple has settled is the counter's output stable.

Harald

6. ### (*steve*)¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥdModerator

25,490
2,832
Jan 21, 2010
A synchronous counter is one where the next state is determined by the inputs at the time the clock pulse arrives.

Compare this to a ripple counter where an input pulse clocks one element. The output of this clocks the next, and so on.

The difference is that one completes all state changes in one step, whereas in the other the changes pass from one chip to the next (rippling through, as the name suggests).

If you look at a 4017, that is a synchronous counter. (It's a Johnson counter -- aka twisted ring counter)

A 4020, 4040, etc are ripple counters. The Q-bar output of flip flops connect to the following clock (toggle) input.