Static Noise Margin Simulation

[rajshri]

Hi,
I am simulating the logic cells for static noise margin using
standard simulation method used for SRAM cells. I have two indepenednt
circuits getting simulated in the same schematic. I am using VCVS in my
circuits. I am observing one circuit affecting on the other! Have any
one experinced this while doing this kind of simulations? I can explain
my problem better if anyone have experience with SNM simulation.
Thanks,
Rajashri

 

[Jim Thompson]

Hi,
I am simulating the logic cells for static noise margin using
standard simulation method used for SRAM cells. I have two indepenednt
circuits getting simulated in the same schematic. I am using VCVS in my
circuits. I am observing one circuit affecting on the other! Have any
one experinced this while doing this kind of simulations? I can explain
my problem better if anyone have experience with SNM simulation.
Thanks,
Rajashri

I can think of a variety of setups to measure static noise margins.

Please post a URL link to a schematic.

...Jim Thompson

 

[rajshri]

Hi,
I am using the schematic posted in this paper.
E. Seevinck, et al, "Static-Noise Margin Analysis of MOS SRAM
Cells", IEEE J.
of Solid-State Circuits, Vol. SC22, No. 5, p.p.748-754, 1987.
I am simulating for master latch and slave latch. Though the
circuits are indepenedent of each other except power and ground, the
results are getting mixed up!
Thanks,
Rajashri

 

[Jim Thompson]

Hi,
I am using the schematic posted in this paper.
E. Seevinck, et al, "Static-Noise Margin Analysis of MOS SRAM
Cells", IEEE J.
of Solid-State Circuits, Vol. SC22, No. 5, p.p.748-754, 1987.
I am simulating for master latch and slave latch. Though the
circuits are indepenedent of each other except power and ground, the
results are getting mixed up!
Thanks,
Rajashri

[snip]

My JSSC saved papers only go back to 1997.

Post your schematic.

...Jim Thompson