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State Transition Diagrams of Counters

Discussion in 'Electronics Homework Help' started by Tman, Oct 24, 2016.

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  1. Tman

    Tman

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    Oct 24, 2016
    I am wondering how to draw a state diagram for a 2 bit counter which includes the same reset capabilities as a register?

    And if the reset signal is asynchronous does this make it a Mealy machine? What would the output of this function be?
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    10,609
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    Nov 17, 2011
    How many states does teh counter have (hint: it is a 2 bit counter...)?
    What is the reset state?
    What are the input signals and how will these signals lead to a change in state?

    Answering these questions will lead to the requested state diagram. Once you have the state diagram look up the difference between a Mealy and a Moore machine to answer the second question.

    I do not understand this question? Which function? Imho the function is given by the "2 bit counter" and therefore the output is straight forward, isn't it?
     
  3. Tman

    Tman

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    Oct 24, 2016
    Thank you
     
  4. Tman

    Tman

    3
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    Oct 24, 2016
    Although I am still confused about the reset state?

    So it goes 00 -> 01 -> 10 -> 11 -> 00 - is this the reset state? from 11 -> 00?
    Does it matter if we are considering jk flip flops or some other flip flop?
     
  5. Harald Kapp

    Harald Kapp Moderator Moderator

    10,609
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    Nov 17, 2011
    The "reset state" is what you define it to be. Any state can be used as the reset state provided the reset signal forces the state machine into this state.
    It is very common, however, to use '00' as the reset state as it is very natural to assume a counter to be reset to zero.
    However, 'zero' doesn't need to be coded by '00'. The assignment of states to numbers is arbitrary and depends on the code scheme used. consider e.g. Gray coding which is rather different from straight binary coding.
    Aside from simply counting, state machines can be used for a lot of different purposes for some of which it may be advantageous to have a reset state other than '00'.

    YOu can answer this question for yourself: design the state machine using D-FFs in one realization, JK-FFs in another realization (not too much work for a 2-bit state machine). Compare the results...
     
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