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ssr's as analog switches

Discussion in 'Electronic Design' started by John Larkin, Oct 22, 2005.

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  1. John Larkin

    John Larkin Guest

    The '4066' thread above reminded me of this question: how good are
    opto-mos solid-state relays as analog switches?

    I recently experimented with a Claire CPC1008N, nice little part. But
    on the board where it was used, it turned out to be the bad-boy for DC
    offset, something we didn't expect. Seems like heating from the led
    causes thermoelectrics in the switch side, on the order of 600 nV per
    mA of led current. This is nasty enough that we plan to replace the
    ssr's with real (latching) relays next rev. We reduced the led drive
    as low as we dared, to about 1.5 mA (it trips around 0.5) and got the
    offset below 1 uV, barely acceptable here.

    Any experience with stuff like this? With leakage?

    I'd do some more experiments, but one would potentially have to test a
    lot of parts, and pcb layout (thermal symmetry issues) would seem to
    matter, much hassle, so we'll just bail to the relay for now.

    I guess that a silicon chip, gold or aluminum wire bonds, and copper
    leads would make a bunch of thermocouples, tens of uV per deg C each,
    and the heat from the led (say, 200 k/w gross thermal resistance?)
    would have to be dumped *very* symmetrically to avoid some terrible

    Hey, any linear IC must have similar problems, especially something
    like an LT1028, fairly high dissipation and low advertised offsets. In
    cases like that, I suppose it just settles to some constant
    thermoelectric offset after a few minutes (if not loaded much) so
    nobody notices. I sometimes use 1028's with very low-value feedback
    networks (to keep Johnson noise down) and add a cheap unity-gain opamp
    inside the loop, after the 1028, just to drive the feedback resistors
    without heating the main chip.

    Relays are wonderful.

  2. John Fields

    John Fields Guest

    I agree, and relays with mercury wetted contacts are even
  3. Phil Hobbs

    Phil Hobbs Guest

    Silicon has a huge TC coefficient with any metal, something like 700
    uV/K IIRC. Common-centroid design, very small dimensions, and the high
    thermal conductivity of silicon help in controlling the TC offsets in ICs.


    Phil Hobbs
  4. Joerg

    Joerg Guest

    Hello John,
    I don't know what you are trying to do over the iso barrier here. Any
    chance to do it with little transformers? Or is it all DC?
    For a while. After that you have to start cracking out that bottle of
    cleaning fluid and thin paper at regular intervals. Then you have to
    open the window in the midst of winter to get rid of the stench. I am
    about ready to open my EMI receiver and replace all the relays in there
    with PIN diodes, FETs or whatever is not mechanical.

    Regards, Joerg
  5. Dave

    Dave Guest

    Not leakage, but I have found one analogue switches injected a very
    significant charge into the circuit, which was a disaster for a laser
    power supply. Changing the switch cured the problem.
  6. Late reply I'm afraid.

    I experienced something similar about a year ago, with
    the I-R PVN012 PhotoMOS switches.

    They were used to select precision pulldown resistors,
    or a 10mA constant current sink, three channels at a time.

    I started to trace why the precision resistors were
    slightly the wrong value, but then noticed that when
    the (single) 10mA current source was switched onto
    a channel then it drifted slightly.... and the rate
    of drift looked suspiciously like it was thermal.

    I then discovered that if the (supposedly) OFF devices
    were unplugged then there was no drift. So the OFF
    switches were leaking somehow, a few 10's of uA that
    took seconds to come up and settle.

    Since it was definitely not thermal, the only thing I
    could think of with a similar time constant was that
    (somehow) the gate-source capacitances of the OFF switches
    were being charged up.

    Strangely enough, putting a bias voltage across the OFF
    switches stopped the leakage.

    Unfortunately this was only a small part of a large system
    being commissioned on-site. So as soon as a 'cure?' had
    been found I had to move on to other things.
  7. Tony Williams wrote...
    The bias voltage you refer to was across the two back-back
    mosfets in the output switch of the "off" ssr? How high
    was the "unbiased" voltage across them when you observed
    the >10uA leakage?
  8. John Larkin

    John Larkin Guest

    Wow, yet another weirdness. Sounds like, maybe, the OFF photofets
    didn't have their gates fully discharged, and they were slowly leaking
    towards zero. I could imagine the floating gate driver getting
    confused for the last few tenths of a volt of turnoff. Or maybe
    getting charged by Cdg.

    The photofets sound like cool parts, and are unless you're working
    with low-level stuff. We're converting a couple of designs back to
    hard relays. You can get a nice tiny sealed surface-mount DPDT
    latching relay for a couple of dollars, and it has specs no
    semiconductor can match.

    Claire does have a new, interesting SSR whose switch side is current
    and thermal-limited; that could be useful as a current limiter alone.

  9. Yes, probably >5v.
    Not measured, but low. A rough guess would be in the
    1v region.
  10. nospam

    nospam Guest

    Kinda hard to see how about 1.5mW of heating effect is going to generate
    thermoelectric effects which are not swamped by enviromental effects like a
    bit of a draft or being a few inches away from a warm chip.

    My understanding of these 'optoMOSFETS' is they are just an LED shining on
    a stack of photodiodes which can generate enough voltage to turn on a
    standard MOSFET (or pair of back to back MOSFETS).

    In such a tiny package I would not be suprised if some of the LED light
    reached the MOSFET and you were seeing a photovoltaic effect.
  11. John Larkin

    John Larkin Guest

    "Common-mode" temperature effects can't generate voltages; you need
    temperature gradients to make thermoelectrics. The fets must be pretty
    close together (the package is tiny) so it would be hard to force much
    of a thermal gradient externally.

    600 mV ain't a lot of voltage, considering that the
    silicon-wirebond-copper system must generate something in the ballpark
    of 50 uV/K.
    The gate driver is actually an IC, with the photoelectric stack as
    part of the circuit. This particular relay is bidirectional, so does
    have two mosfets back-to-back.
    The effect we measured had a longish time constant, 15 seconds or so,
    and the magnitude was pretty much proportional to LED drive current,
    so we figured it was likely thermoelectric..

  12. John Larkin

    John Larkin Guest

    Oops, 600 nV.

  13. Fred Bloggs

    Fred Bloggs Guest

    IR has already gone down this road and with a line of "MicroRelays" with
    guaranteed "Thermal Offset." The selection chart may say 0.2V but the
    datasheets say 0.2uV. These are specifically targeted for low thermal
    offset apps like switching thermocouples:
    and for example.
    They all have the same line.
    I notice your CPC1008N datasheet has no such characterization.
  14. John Larkin

    John Larkin Guest

    200 nV at 5 mA is nice... it's probably less at 2 mA, enough to
    operate the thing.

    But it looks like we'll stick with a latching relay for now.

  15. Tony Williams wrote...

    I note the pvn012 is a 100-milliohm max device, which means
    it's made using two probably rather-large 25-milliohm typ
    MOSFETs in opposed-series, such as the die used in IR's
    IRF7402 50-milliohm max (at Vgs = 2.7V) 20V n-channel part.

    This FET has 900pF of gate capacitance at 1V, and two wired
    in parallel as in the pvn012 means the relay's photodiode
    stack has to drive 1800pF. Its 5ms turn-on time implies
    several uA of photocurrent into 3V, which is reasonable,
    but the faster 0.5ms turn-off time implies a much higher
    pulldown current, when the photodiodes are basically open.

    I believe this is obtained using a PNP emitter follower,
    somewhat like this,

    .. opto-isolated MOSFET relays
    .. ,-----o
    .. LED 4V PD stack |--'
    .. o---, ,----+--|>|--+------+---||<-,
    .. _|_ | | | | |--+
    .. _\_/_ --> _V_ | |/V | |
    .. | | '-----| ,--|-------+-----o
    .. o---' _V_ |\ | | |
    .. | | | | |--+
    .. '------------+---' '---||<-'
    .. |--,
    .. '-----o

    Such a circuit when OFF would still leave a small voltage on
    the 1800pF gate capacitance of the MOSFETs, say about 400mV.
    This would not be a problem with an ordinary MOSFET die used
    in an opto-relay, even considering the sub-threshold current
    issue, but for a logic-level MOSFET die, it might well bias
    enough FET current flow to be a problem in some applications.
    A 10uA current is only 1ppm of the 10A rating for this FET.
    It takes -2 to -3 volts of gate-voltage change in most n-FETs
    to get a factor of 1E6 in drain current. Glancing at some
    eight-decade drain-current plots of subthreshold operation
    I've made for various MOSFETs, a 1ppm current at Vgs = 400mV
    isn't at all surprising.

    This story doesn't explain why the "off" drain current would
    go away at high drain voltages, although we know all the FET's
    capacitances are much lower under this condition, e.g. Coss =
    270pF at 15V, compared to 900pF at 1V, so we'd expect a faster
    settling time to low currents.

    This issue could be solved if they added a gate resistor, but
    perhaps such a part is inconvenient for these devices. They
    may have gotten used to getting away with some residual gate
    voltage in the older designs using higher-gate-voltage MOSFETs.
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