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SSO noise simulation with spectre (or spice)

Discussion in 'Electronic Design' started by Ian, Aug 20, 2004.

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  1. Ian

    Ian Guest

    Hi all,

    I am wondering has anyone here any experience with Simultaneous
    Switching Outputs simulations at the chip level.

    I can build a schematic of my complete ring , and give input stimuli of
    what i expect my data inputs to look like. I can also of course use the
    extreacted layout, and include a model of the package which I will use.

    I will then have , say, 64 data outputs switching at the same time, some
    pulling up and some pulling down.

    The question is how can I measure the switching noise now and the
    influence this will have on anything?

    thanks a lot.
     
  2. Mike

    Mike Guest

    Why not look at the power and ground on chip? You've got the ring modeled,
    so the information about the core power and ground when the outputs switch
    should be available.

    As for the influence, that depends on the circuit. You're better suited
    than I am to decide what tests would be most applicable.

    By the way, I'm currently doing the same analysis for a chip I'm working
    on. In my case, though, I'm doing the analysis before there's any layout. I
    don't get post-layout parasitics this way, but I'll know what's required
    before I start layout, so the rework required will be zero.

    -- Mike --
     
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